MPCC_OGAM_RAMB_END_CNTL1_G  302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
MPCC_OGAM_RAMB_END_CNTL1_G   60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
MPCC_OGAM_RAMB_END_CNTL1_G  110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \