MPCC_OGAM_RAMA_START_CNTL_R  323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
MPCC_OGAM_RAMA_START_CNTL_R   40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
MPCC_OGAM_RAMA_START_CNTL_R   90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \