MPCC_OGAM_RAMA_START_CNTL_B  321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
MPCC_OGAM_RAMA_START_CNTL_B   38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
MPCC_OGAM_RAMA_START_CNTL_B   88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \