MPCC_OGAM_RAMA_END_CNTL2_R  332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);
MPCC_OGAM_RAMA_END_CNTL2_R   49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
MPCC_OGAM_RAMA_END_CNTL2_R   99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \