MPCC_OGAM_RAMA_END_CNTL2_G  330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);
MPCC_OGAM_RAMA_END_CNTL2_G   47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
MPCC_OGAM_RAMA_END_CNTL2_G   97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \