MPCC_OGAM_RAMA_END_CNTL1_B  327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
MPCC_OGAM_RAMA_END_CNTL1_B   44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
MPCC_OGAM_RAMA_END_CNTL1_B   94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \