MPCC_OGAM_MODE    372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
MPCC_OGAM_MODE    385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
MPCC_OGAM_MODE    399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
MPCC_OGAM_MODE    404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
MPCC_OGAM_MODE    427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
MPCC_OGAM_MODE     70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
MPCC_OGAM_MODE    120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
MPCC_OGAM_MODE    168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
MPCC_OGAM_MODE    214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	type MPCC_OGAM_MODE;\