max_ln_count      120 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
max_ln_count      150 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
max_ln_count      944 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
max_ln_count     2836 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	link->dpcd_caps.max_ln_count.raw = dpcd_data[
max_ln_count     2843 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
max_ln_count      927 drivers/gpu/drm/amd/display/dc/dc.h 	union max_lane_count max_ln_count;