MPCC_OGAM_LUT_RAM_CONTROL  253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
MPCC_OGAM_LUT_RAM_CONTROL  266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
MPCC_OGAM_LUT_RAM_CONTROL   68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
MPCC_OGAM_LUT_RAM_CONTROL  118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\