max_lanes 640 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u32 max_lanes, u32 max_rate) max_lanes 670 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.lane_count > max_lanes) max_lanes 671 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = max_lanes; max_lanes 374 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) max_lanes 376 drivers/gpu/drm/gma500/cdv_intel_dp.c return (max_link_clock * max_lanes * 19) / 20; max_lanes 516 drivers/gpu/drm/gma500/cdv_intel_dp.c int max_lanes = cdv_intel_dp_max_lane_count(encoder); max_lanes 530 drivers/gpu/drm/gma500/cdv_intel_dp.c > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))) max_lanes 535 drivers/gpu/drm/gma500/cdv_intel_dp.c > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)) max_lanes 2237 drivers/gpu/drm/i915/display/intel_ddi.c if (port == PORT_A && intel_dig_port->max_lanes == 4) max_lanes 4248 drivers/gpu/drm/i915/display/intel_ddi.c int max_lanes = 4; max_lanes 4251 drivers/gpu/drm/i915/display/intel_ddi.c return max_lanes; max_lanes 4255 drivers/gpu/drm/i915/display/intel_ddi.c max_lanes = port == PORT_A ? 4 : 0; max_lanes 4258 drivers/gpu/drm/i915/display/intel_ddi.c max_lanes = 2; max_lanes 4269 drivers/gpu/drm/i915/display/intel_ddi.c max_lanes = 4; max_lanes 4272 drivers/gpu/drm/i915/display/intel_ddi.c return max_lanes; max_lanes 4345 drivers/gpu/drm/i915/display/intel_ddi.c intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); max_lanes 1262 drivers/gpu/drm/i915/display/intel_display_types.h u8 max_lanes; max_lanes 220 drivers/gpu/drm/i915/display/intel_dp.c int source_max = intel_dig_port->max_lanes; max_lanes 240 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_max_data_rate(int max_link_clock, int max_lanes) max_lanes 248 drivers/gpu/drm/i915/display/intel_dp.c return max_link_clock * max_lanes; max_lanes 597 drivers/gpu/drm/i915/display/intel_dp.c int max_rate, mode_rate, max_lanes, max_link_clock; max_lanes 618 drivers/gpu/drm/i915/display/intel_dp.c max_lanes = intel_dp_max_lane_count(intel_dp); max_lanes 620 drivers/gpu/drm/i915/display/intel_dp.c max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); max_lanes 638 drivers/gpu/drm/i915/display/intel_dp.c max_lanes, max_lanes 7152 drivers/gpu/drm/i915/display/intel_dp.c if (WARN(intel_dig_port->max_lanes < 1, max_lanes 7154 drivers/gpu/drm/i915/display/intel_dp.c intel_dig_port->max_lanes, port_name(port))) max_lanes 7307 drivers/gpu/drm/i915/display/intel_dp.c intel_dig_port->max_lanes = 4; max_lanes 109 drivers/gpu/drm/i915/display/intel_dp.h int intel_dp_max_data_rate(int max_link_clock, int max_lanes); max_lanes 432 drivers/gpu/drm/i915/display/intel_dp_mst.c int max_rate, mode_rate, max_lanes, max_link_clock; max_lanes 441 drivers/gpu/drm/i915/display/intel_dp_mst.c max_lanes = intel_dp_max_lane_count(intel_dp); max_lanes 443 drivers/gpu/drm/i915/display/intel_dp_mst.c max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); max_lanes 3080 drivers/gpu/drm/i915/display/intel_hdmi.c if (WARN(intel_dig_port->max_lanes < 4, max_lanes 3082 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->max_lanes, port_name(port))) max_lanes 3236 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->max_lanes = 4; max_lanes 264 drivers/gpu/drm/i915/display/intel_tc.c int max_lanes; max_lanes 276 drivers/gpu/drm/i915/display/intel_tc.c max_lanes = intel_tc_port_fia_max_lane_count(dig_port); max_lanes 278 drivers/gpu/drm/i915/display/intel_tc.c WARN_ON(max_lanes != 4); max_lanes 294 drivers/gpu/drm/i915/display/intel_tc.c if (max_lanes < required_lanes) { max_lanes 297 drivers/gpu/drm/i915/display/intel_tc.c max_lanes, required_lanes); max_lanes 75 drivers/media/platform/cadence/cdns-csi2rx.c u8 max_lanes; max_lanes 130 drivers/media/platform/cadence/cdns-csi2rx.c for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { max_lanes 132 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->max_lanes); max_lanes 323 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->max_lanes = dev_cfg & 7; max_lanes 324 drivers/media/platform/cadence/cdns-csi2rx.c if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { max_lanes 326 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->max_lanes); max_lanes 391 drivers/media/platform/cadence/cdns-csi2rx.c if (csi2rx->num_lanes > csi2rx->max_lanes) { max_lanes 465 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, max_lanes 116 drivers/media/platform/cadence/cdns-csi2tx.c unsigned int max_lanes; max_lanes 461 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->max_lanes = dev_cfg & CSI2TX_DEVICE_CONFIG_LANES_MASK; max_lanes 462 drivers/media/platform/cadence/cdns-csi2tx.c if (csi2tx->max_lanes > CSI2TX_LANES_MAX) { max_lanes 464 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->max_lanes); max_lanes 516 drivers/media/platform/cadence/cdns-csi2tx.c if (csi2tx->num_lanes > csi2tx->max_lanes) { max_lanes 623 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams,