max_lane           59 drivers/gpu/drm/msm/edp/edp.h void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane);
max_lane          406 drivers/gpu/drm/msm/edp/edp_ctrl.c 	u8 max_lane = ctrl->dp_link.num_lanes;
max_lane          425 drivers/gpu/drm/msm/edp/edp_ctrl.c 	for (lane = 1; lane <= max_lane; lane <<= 1) {
max_lane          699 drivers/gpu/drm/msm/edp/edp_ctrl.c 	u8 rate, lane, max_lane;
max_lane          704 drivers/gpu/drm/msm/edp/edp_ctrl.c 	max_lane = ctrl->dp_link.num_lanes;
max_lane          717 drivers/gpu/drm/msm/edp/edp_ctrl.c 		if (lane >= 1 && lane < max_lane)
max_lane           68 drivers/gpu/drm/msm/edp/edp_phy.c void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane)
max_lane           78 drivers/gpu/drm/msm/edp/edp_phy.c 	for (i = 0; i < max_lane; i++)
max_lane           83 drivers/gpu/drm/msm/edp/edp_phy.c 	for (i = max_lane; i < EDP_MAX_LANE; i++)