max_irr          1096 arch/x86/include/asm/kvm_host.h 	void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
max_irr           385 arch/x86/kvm/lapic.c bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
max_irr           392 arch/x86/kvm/lapic.c 	*max_irr = -1;
max_irr           407 arch/x86/kvm/lapic.c 			*max_irr = __fls(irr_val) + vec;
max_irr           411 arch/x86/kvm/lapic.c 		(max_updated_irr == *max_irr));
max_irr           415 arch/x86/kvm/lapic.c bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
max_irr           419 arch/x86/kvm/lapic.c 	return __kvm_apic_update_irr(pir, apic->regs, max_irr);
max_irr          2572 arch/x86/kvm/lapic.c 	int max_irr, max_isr;
max_irr          2581 arch/x86/kvm/lapic.c 	max_irr = apic_find_highest_irr(apic);
max_irr          2582 arch/x86/kvm/lapic.c 	if (max_irr < 0)
max_irr          2583 arch/x86/kvm/lapic.c 		max_irr = 0;
max_irr          2587 arch/x86/kvm/lapic.c 	data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
max_irr            87 arch/x86/kvm/lapic.h bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
max_irr            88 arch/x86/kvm/lapic.h bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
max_irr          5164 arch/x86/kvm/svm.c static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
max_irr          3409 arch/x86/kvm/vmx/nested.c 	int max_irr;
max_irr          3420 arch/x86/kvm/vmx/nested.c 	max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
max_irr          3421 arch/x86/kvm/vmx/nested.c 	if (max_irr != 256) {
max_irr          3427 arch/x86/kvm/vmx/nested.c 			vapic_page, &max_irr);
max_irr          3429 arch/x86/kvm/vmx/nested.c 		if ((u8)max_irr > ((u8)status & 0xff)) {
max_irr          3431 arch/x86/kvm/vmx/nested.c 			status |= (u8)max_irr;
max_irr          6119 arch/x86/kvm/vmx/vmx.c static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
max_irr          6130 arch/x86/kvm/vmx/vmx.c 		vmx_set_rvi(max_irr);
max_irr          6136 arch/x86/kvm/vmx/vmx.c 	int max_irr;
max_irr          6148 arch/x86/kvm/vmx/vmx.c 			kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
max_irr          6165 arch/x86/kvm/vmx/vmx.c 		max_irr = kvm_lapic_find_highest_irr(vcpu);
max_irr          6167 arch/x86/kvm/vmx/vmx.c 	vmx_hwapic_irr_update(vcpu, max_irr);
max_irr          6168 arch/x86/kvm/vmx/vmx.c 	return max_irr;
max_irr          7548 arch/x86/kvm/x86.c 	int max_irr, tpr;
max_irr          7560 arch/x86/kvm/x86.c 		max_irr = kvm_lapic_find_highest_irr(vcpu);
max_irr          7562 arch/x86/kvm/x86.c 		max_irr = -1;
max_irr          7564 arch/x86/kvm/x86.c 	if (max_irr != -1)
max_irr          7565 arch/x86/kvm/x86.c 		max_irr >>= 4;
max_irr          7569 arch/x86/kvm/x86.c 	kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);