MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL  164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL  165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL  166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\