MPCC_OGAM 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\ MPCC_OGAM 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\ MPCC_OGAM 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\ MPCC_OGAM 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\ MPCC_OGAM 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\ MPCC_OGAM 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\ MPCC_OGAM 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\ MPCC_OGAM 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\ MPCC_OGAM 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\ MPCC_OGAM 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\ MPCC_OGAM 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\ MPCC_OGAM 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\ MPCC_OGAM 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\ MPCC_OGAM 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\ MPCC_OGAM 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\ MPCC_OGAM 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\ MPCC_OGAM 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\ MPCC_OGAM 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\ MPCC_OGAM 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\ MPCC_OGAM 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\ MPCC_OGAM 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\ MPCC_OGAM 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\ MPCC_OGAM 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\ MPCC_OGAM 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\ MPCC_OGAM 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\ MPCC_OGAM 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\ MPCC_OGAM 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\ MPCC_OGAM 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\ MPCC_OGAM 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\ MPCC_OGAM 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\ MPCC_OGAM 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\ MPCC_OGAM 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)