MPCC_MODE         210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
MPCC_MODE         214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
MPCC_MODE         235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 						MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
MPCC_MODE         304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 						MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
MPCC_MODE         441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
MPCC_MODE          63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
MPCC_MODE          86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	type MPCC_MODE;\