MPCC_MEM_PWR_CTRL  242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
MPCC_MEM_PWR_CTRL   66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
MPCC_MEM_PWR_CTRL  116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\