MPCC_CONTROL 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE_5(MPCC_CONTROL[mpcc_id], MPCC_CONTROL 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING); MPCC_CONTROL 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY); MPCC_CONTROL 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], MPCC_CONTROL 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id], MPCC_CONTROL 441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, MPCC_CONTROL 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_CONTROL, MPCC, inst),\ MPCC_CONTROL 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_CONTROL[MAX_MPCC]; \ MPCC_CONTROL 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE_7(MPCC_CONTROL[mpcc_id],