max_handles 814 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c handle.uvd_max_handles = adev->uvd.max_handles; max_handles 205 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; max_handles 226 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; max_handles 245 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; max_handles 251 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; max_handles 267 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { max_handles 354 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) max_handles 358 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c if (i == adev->uvd.max_handles) max_handles 424 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { max_handles 746 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { max_handles 770 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { max_handles 785 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) max_handles 1281 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c for (i = 0; i < adev->uvd.max_handles; ++i) { max_handles 57 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h unsigned max_handles; max_handles 559 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; max_handles 276 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); max_handles 602 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); max_handles 610 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); max_handles 704 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); max_handles 840 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); max_handles 1673 drivers/gpu/drm/radeon/radeon.h unsigned max_handles; max_handles 138 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; max_handles 166 drivers/gpu/drm/radeon/radeon_uvd.c rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; max_handles 186 drivers/gpu/drm/radeon/radeon_uvd.c RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; max_handles 219 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { max_handles 256 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { max_handles 331 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { max_handles 516 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < p->rdev->uvd.max_handles; ++i) { max_handles 542 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < p->rdev->uvd.max_handles; ++i) { max_handles 557 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < p->rdev->uvd.max_handles; ++i) max_handles 859 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rdev->uvd.max_handles; ++i) { max_handles 133 drivers/gpu/drm/radeon/uvd_v1_0.c (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; max_handles 125 drivers/gpu/drm/radeon/uvd_v2_2.c (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; max_handles 62 drivers/gpu/drm/radeon/uvd_v4_2.c (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; max_handles 75 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);