MPCC_BG_R_CR       54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_SET(MPCC_BG_R_CR[mpcc_id], 0,
MPCC_BG_R_CR       55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_BG_R_CR, bg_r_cr);
MPCC_BG_R_CR       40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SRII(MPCC_BG_R_CR, MPCC, inst),\
MPCC_BG_R_CR       55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
MPCC_BG_R_CR       73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
MPCC_BG_R_CR       96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	type MPCC_BG_R_CR;\