MPCC_BG_G_Y        56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_SET(MPCC_BG_G_Y[mpcc_id], 0,
MPCC_BG_G_Y        57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_BG_G_Y, bg_g_y);
MPCC_BG_G_Y        39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SRII(MPCC_BG_G_Y, MPCC, inst),\
MPCC_BG_G_Y        54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
MPCC_BG_G_Y        72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
MPCC_BG_G_Y        95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	type MPCC_BG_G_Y;\