MPCC0_MPCC_SM_CONTROL   75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
MPCC0_MPCC_SM_CONTROL   76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
MPCC0_MPCC_SM_CONTROL   77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
MPCC0_MPCC_SM_CONTROL   78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
MPCC0_MPCC_SM_CONTROL   79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
MPCC0_MPCC_SM_CONTROL   80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\