MPCC0_MPCC_CONTROL   63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
MPCC0_MPCC_CONTROL   64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
MPCC0_MPCC_CONTROL   65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
MPCC0_MPCC_CONTROL   66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
MPCC0_MPCC_CONTROL   67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
MPCC0_MPCC_CONTROL   68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
MPCC0_MPCC_CONTROL  132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
MPCC0_MPCC_CONTROL  133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\