MPCC 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_TOP_SEL, MPCC, inst),\ MPCC 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BOT_SEL, MPCC, inst),\ MPCC 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_CONTROL, MPCC, inst),\ MPCC 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_STATUS, MPCC, inst),\ MPCC 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_OPP_ID, MPCC, inst),\ MPCC 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_G_Y, MPCC, inst),\ MPCC 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_R_CR, MPCC, inst),\ MPCC 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_B_CB, MPCC, inst),\ MPCC 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_B_CB, MPCC, inst),\ MPCC 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_SM_CONTROL, MPCC, inst) MPCC 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_TOP_GAIN, MPCC, inst),\ MPCC 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\ MPCC 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\ MPCC 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\