MP1_SMN_C2PMSG_83 77 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c REG_WRITE(MP1_SMN_C2PMSG_83, param); MP1_SMN_C2PMSG_83 85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c return REG_READ(MP1_SMN_C2PMSG_83); MP1_SMN_C2PMSG_83 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000; MP1_SMN_C2PMSG_83 62 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c REG_WRITE(MP1_SMN_C2PMSG_83, param); MP1_SMN_C2PMSG_83 70 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c return REG_READ(MP1_SMN_C2PMSG_83); MP1_SMN_C2PMSG_83 96 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \ MP1_SMN_C2PMSG_83 120 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ MP1_SMN_C2PMSG_83 183 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h uint32_t MP1_SMN_C2PMSG_83;