MP1_BASE           41 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
MP1_BASE           41 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
MP1_BASE           41 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
MP1_BASE           41 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
MP1_BASE           41 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
MP1_BASE           41 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
MP1_BASE           42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c static const struct IP_BASE MP1_BASE  = { { { { 0x00016000, 0, 0, 0, 0 } },
MP1_BASE           63 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
MP1_BASE          103 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
MP1_BASE           91 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
MP1_BASE          123 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } },
MP1_BASE          123 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
MP1_BASE          158 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
MP1_BASE           63 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MP1_BASE			= { { { { 0x00016000, 0, 0, 0, 0 } },
MP1_BASE           93 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },