MP1                60 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
MP1                68 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
MP1                78 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                88 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
MP1               102 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               133 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               135 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
MP1                49 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
MP1                57 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
MP1                67 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                77 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
MP1                91 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               121 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               123 drivers/gpu/drm/amd/powerplay/smu_v12_0.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
MP1                54 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                59 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                67 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
MP1                76 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
MP1                85 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               103 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               105 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
MP1                64 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                72 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                86 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
MP1               104 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               130 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               132 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
MP1               147 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
MP1                73 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                78 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
MP1                92 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
MP1               110 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               136 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
MP1               138 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
MP1               153 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);