MP0_BASE 40 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); MP0_BASE 40 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); MP0_BASE 40 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); MP0_BASE 40 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); MP0_BASE 40 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); MP0_BASE 40 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); MP0_BASE 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) MP0_BASE 95 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, MP0_BASE 85 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, MP0_BASE 116 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, MP0_BASE 116 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, MP0_BASE 151 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } }, MP0_BASE 58 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, MP0_BASE 87 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },