max_clks_state    207 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
max_clks_state    215 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	if (low_req_clk > clk_mgr_dce->max_clks_state) {
max_clks_state    217 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
max_clks_state    221 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			low_req_clk = clk_mgr_dce->max_clks_state;
max_clks_state    458 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
max_clks_state    460 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
max_clks_state    226 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
max_clks_state    234 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (low_req_clk > clk_mgr_dce->max_clks_state) {
max_clks_state    236 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
max_clks_state    240 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			low_req_clk = clk_mgr_dce->max_clks_state;
max_clks_state    832 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state;
max_clks_state    834 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
max_clks_state    260 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 	enum dm_pp_clocks_state max_clks_state;