max_clk 59 arch/x86/include/asm/intel-mid.h u32 max_clk; max_clk 428 arch/x86/platform/intel-mid/sfi.c sd_info.max_clk = pentry->max_freq; max_clk 433 arch/x86/platform/intel-mid/sfi.c sd_info.max_clk, max_clk 1175 drivers/gpu/drm/bridge/sil-sii8620.c int max_clk; max_clk 1192 drivers/gpu/drm/bridge/sil-sii8620.c if (clk < clk_spec[i].max_clk) max_clk 1195 drivers/gpu/drm/bridge/sil-sii8620.c if (100 * clk >= 98 * clk_spec[i].max_clk) max_clk 499 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_set_rate(mdp4_kms->clk, config->max_clk); max_clk 501 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_set_rate(mdp4_kms->lut_clk, config->max_clk); max_clk 576 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c config.max_clk = 266667000; max_clk 48 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h uint32_t max_clk; max_clk 98 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 200000000, max_clk 180 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 200000000, max_clk 275 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 320000000, max_clk 342 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 320000000, max_clk 437 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 400000000, max_clk 545 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 412500000, max_clk 630 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 320000000, max_clk 738 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .max_clk = 412500000, max_clk 97 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t max_clk; max_clk 1000 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); max_clk 154 drivers/mmc/host/bcm2835.c unsigned int max_clk; /* Max possible freq */ max_clk 1135 drivers/mmc/host/bcm2835.c div = host->max_clk / clock; max_clk 1138 drivers/mmc/host/bcm2835.c if ((host->max_clk / div) > clock) max_clk 1145 drivers/mmc/host/bcm2835.c clock = host->max_clk / (div + 2); max_clk 1272 drivers/mmc/host/bcm2835.c if (!mmc->f_max || mmc->f_max > host->max_clk) max_clk 1273 drivers/mmc/host/bcm2835.c mmc->f_max = host->max_clk; max_clk 1274 drivers/mmc/host/bcm2835.c mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; max_clk 1408 drivers/mmc/host/bcm2835.c host->max_clk = clk_get_rate(clk); max_clk 175 drivers/mmc/host/sdhci-cadence.c return host->max_clk; max_clk 37 drivers/mmc/host/sdhci-cns3xxx.c while (host->max_clk / div > clock) { max_clk 51 drivers/mmc/host/sdhci-cns3xxx.c clock, host->max_clk / div); max_clk 194 drivers/mmc/host/sdhci-of-arasan.c sdhci_set_clock(host, host->max_clk); max_clk 68 drivers/mmc/host/sdhci-of-aspeed.c if (WARN_ON(clock > host->max_clk)) max_clk 69 drivers/mmc/host/sdhci-of-aspeed.c clock = host->max_clk; max_clk 34 drivers/mmc/host/sdhci-of-esdhc.c const unsigned int max_clk[MMC_TIMING_NUM]; max_clk 39 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_MMC_HS] = 46500000, max_clk 40 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_SD_HS] = 46500000, max_clk 45 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, max_clk 46 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_MMC_HS200] = 167000000, max_clk 51 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, max_clk 52 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_MMC_HS200] = 125000000, max_clk 57 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_LEGACY] = 20000000, max_clk 58 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_MMC_HS] = 42000000, max_clk 59 drivers/mmc/host/sdhci-of-esdhc.c .max_clk[MMC_TIMING_SD_HS] = 40000000, max_clk 620 drivers/mmc/host/sdhci-of-esdhc.c fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; max_clk 630 drivers/mmc/host/sdhci-of-esdhc.c while (host->max_clk / pre_div / 16 > clock && pre_div < 256) max_clk 633 drivers/mmc/host/sdhci-of-esdhc.c while (host->max_clk / pre_div / div > clock && div < 16) max_clk 657 drivers/mmc/host/sdhci-of-esdhc.c clock, host->max_clk / pre_div / div); max_clk 658 drivers/mmc/host/sdhci-of-esdhc.c host->mmc->actual_clock = host->max_clk / pre_div / div; max_clk 1051 drivers/mmc/host/sdhci-of-esdhc.c clk = host->max_clk / (esdhc->div_ratio + 1); max_clk 261 drivers/mmc/host/sdhci-s3c.c host->max_clk = ourhost->clk_rates[best_src]; max_clk 752 drivers/mmc/host/sdhci-tegra.c host->max_clk = host_clk; max_clk 754 drivers/mmc/host/sdhci-tegra.c host->max_clk = clk_get_rate(pltfm_host->clk); max_clk 1574 drivers/mmc/host/sdhci.c if ((host->max_clk * host->clk_mul / div) max_clk 1578 drivers/mmc/host/sdhci.c if ((host->max_clk * host->clk_mul / div) <= clock) { max_clk 1598 drivers/mmc/host/sdhci.c if (host->max_clk <= clock) max_clk 1603 drivers/mmc/host/sdhci.c if ((host->max_clk / div) <= clock) max_clk 1610 drivers/mmc/host/sdhci.c && !div && host->max_clk <= 25000000) max_clk 1616 drivers/mmc/host/sdhci.c if ((host->max_clk / div) <= clock) max_clk 1625 drivers/mmc/host/sdhci.c *actual_clock = (host->max_clk * clk_mul) / real_div; max_clk 3727 drivers/mmc/host/sdhci.c u32 max_clk; max_clk 3866 drivers/mmc/host/sdhci.c host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) max_clk 3869 drivers/mmc/host/sdhci.c host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) max_clk 3872 drivers/mmc/host/sdhci.c host->max_clk *= 1000000; max_clk 3873 drivers/mmc/host/sdhci.c if (host->max_clk == 0 || host->quirks & max_clk 3881 drivers/mmc/host/sdhci.c host->max_clk = host->ops->get_max_clock(host); max_clk 3903 drivers/mmc/host/sdhci.c max_clk = host->max_clk; max_clk 3909 drivers/mmc/host/sdhci.c max_clk = host->max_clk * host->clk_mul; max_clk 3914 drivers/mmc/host/sdhci.c mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; max_clk 3916 drivers/mmc/host/sdhci.c mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; max_clk 3918 drivers/mmc/host/sdhci.c if (!mmc->f_max || mmc->f_max > max_clk) max_clk 3919 drivers/mmc/host/sdhci.c mmc->f_max = max_clk; max_clk 525 drivers/mmc/host/sdhci.h unsigned int max_clk; /* Max possible freq (MHz) */