max_chunks_non_fbc_mode 399 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h i, data->max_chunks_non_fbc_mode[i]); max_chunks_non_fbc_mode 866 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->max_chunks_non_fbc_mode[i] = 128 - dmif_chunk_buff_margin; max_chunks_non_fbc_mode 869 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->max_chunks_non_fbc_mode[i] = 16 - dmif_chunk_buff_margin; max_chunks_non_fbc_mode 912 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size))); max_chunks_non_fbc_mode 915 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size)); max_chunks_non_fbc_mode 375 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces];