MMMC_VM_MX_L1_TLB_CNTL  103 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
MMMC_VM_MX_L1_TLB_CNTL  104 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
MMMC_VM_MX_L1_TLB_CNTL  105 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
MMMC_VM_MX_L1_TLB_CNTL  107 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
MMMC_VM_MX_L1_TLB_CNTL  109 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
MMMC_VM_MX_L1_TLB_CNTL  110 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
MMMC_VM_MX_L1_TLB_CNTL  280 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
MMMC_VM_MX_L1_TLB_CNTL  281 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,