ACPILevel         274 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     SMU71_Discrete_ACPILevel             ACPILevel;
ACPILevel         269 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	SMU72_Discrete_ACPILevel            ACPILevel;
ACPILevel         253 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h     SMU73_Discrete_ACPILevel            ACPILevel;
ACPILevel         285 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	SMU74_Discrete_ACPILevel            ACPILevel;
ACPILevel         291 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	SMU75_Discrete_ACPILevel            ACPILevel;
ACPILevel         327 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     SMU7_Discrete_ACPILevel             ACPILevel;
ACPILevel         234 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h     SMU7_Fusion_ACPILevel             ACPILevel;
ACPILevel        1390 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        1393 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
ACPILevel        1395 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
ACPILevel        1397 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
ACPILevel        1399 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
ACPILevel        1403 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->ACPILevel.SclkFrequency,  &dividers);
ACPILevel        1409 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
ACPILevel        1410 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
ACPILevel        1411 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        1420 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
ACPILevel        1421 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
ACPILevel        1422 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
ACPILevel        1423 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
ACPILevel        1424 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
ACPILevel        1425 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
ACPILevel        1426 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        1427 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        1430 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
ACPILevel        1432 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
ACPILevel        1433 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
ACPILevel        1434 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
ACPILevel        1435 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
ACPILevel        1436 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
ACPILevel        1437 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
ACPILevel        1438 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
ACPILevel        1439 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
ACPILevel        1440 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
ACPILevel        1444 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
ACPILevel        1445 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
ACPILevel        1314 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        1319 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->ACPILevel.SclkFrequency =
ACPILevel        1323 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->ACPILevel.SclkFrequency,
ACPILevel        1324 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				(uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
ACPILevel        1330 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->ACPILevel.SclkFrequency =
ACPILevel        1332 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->ACPILevel.MinVoltage =
ACPILevel        1338 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			table->ACPILevel.SclkFrequency,  &dividers);
ACPILevel        1343 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
ACPILevel        1344 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
ACPILevel        1345 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        1354 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
ACPILevel        1355 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
ACPILevel        1356 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
ACPILevel        1357 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
ACPILevel        1358 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
ACPILevel        1359 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
ACPILevel        1360 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        1361 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        1363 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
ACPILevel        1364 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
ACPILevel        1365 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
ACPILevel        1366 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
ACPILevel        1367 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
ACPILevel        1368 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
ACPILevel        1369 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
ACPILevel        1370 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
ACPILevel        1371 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
ACPILevel        1372 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
ACPILevel        1373 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
ACPILevel        1438 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        1441 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
ACPILevel        1443 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
ACPILevel        1445 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
ACPILevel        1447 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
ACPILevel        1451 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->ACPILevel.SclkFrequency,  &dividers);
ACPILevel        1457 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
ACPILevel        1458 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
ACPILevel        1459 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        1468 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
ACPILevel        1469 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
ACPILevel        1470 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
ACPILevel        1471 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
ACPILevel        1472 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
ACPILevel        1473 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
ACPILevel        1474 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        1475 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        1479 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
ACPILevel        1481 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
ACPILevel        1482 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
ACPILevel        1483 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
ACPILevel        1484 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
ACPILevel        1485 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
ACPILevel        1486 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
ACPILevel        1487 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
ACPILevel        1488 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
ACPILevel        1489 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
ACPILevel        1492 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
ACPILevel        1493 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
ACPILevel        1210 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        1218 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			&table->ACPILevel.MinVoltage, &mvdd);
ACPILevel        1224 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
ACPILevel        1227 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        1228 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        1229 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        1231 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
ACPILevel        1232 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
ACPILevel        1233 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
ACPILevel        1234 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
ACPILevel        1236 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
ACPILevel        1237 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
ACPILevel        1238 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
ACPILevel        1239 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
ACPILevel        1240 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
ACPILevel        1241 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
ACPILevel        1242 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
ACPILevel        1243 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
ACPILevel        1244 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
ACPILevel        1245 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
ACPILevel        1189 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        1191 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.MinVoltage =
ACPILevel        1195 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
ACPILevel        1199 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->ACPILevel.SclkFrequency,  &dividers);
ACPILevel        1206 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
ACPILevel        1207 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
ACPILevel        1208 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        1217 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
ACPILevel        1218 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
ACPILevel        1219 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
ACPILevel        1220 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
ACPILevel        1221 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
ACPILevel        1222 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
ACPILevel        1223 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        1224 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        1228 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
ACPILevel        1230 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
ACPILevel        1231 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
ACPILevel        1232 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
ACPILevel        1233 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
ACPILevel        1234 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
ACPILevel        1235 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
ACPILevel        1236 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
ACPILevel        1237 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
ACPILevel        1238 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
ACPILevel        1119 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        1127 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			&table->ACPILevel.MinVoltage, &mvdd);
ACPILevel        1134 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			&(table->ACPILevel.SclkSetting));
ACPILevel        1139 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        1140 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        1141 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        1143 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
ACPILevel        1144 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
ACPILevel        1145 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
ACPILevel        1146 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
ACPILevel        1148 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
ACPILevel        1149 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
ACPILevel        1150 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
ACPILevel        1151 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
ACPILevel        1152 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
ACPILevel        1153 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
ACPILevel        1154 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
ACPILevel        1155 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
ACPILevel        1156 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
ACPILevel        1157 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
ACPILevel        3001 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
ACPILevel        3004 drivers/gpu/drm/radeon/ci_dpm.c 		table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
ACPILevel        3006 drivers/gpu/drm/radeon/ci_dpm.c 		table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
ACPILevel        3008 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
ACPILevel        3010 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
ACPILevel        3014 drivers/gpu/drm/radeon/ci_dpm.c 					     table->ACPILevel.SclkFrequency, false, &dividers);
ACPILevel        3018 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SclkDid = (u8)dividers.post_divider;
ACPILevel        3019 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
ACPILevel        3020 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.DeepSleepDivId = 0;
ACPILevel        3028 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
ACPILevel        3029 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
ACPILevel        3030 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
ACPILevel        3031 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
ACPILevel        3032 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
ACPILevel        3033 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
ACPILevel        3034 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CcPwrDynRm = 0;
ACPILevel        3035 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CcPwrDynRm1 = 0;
ACPILevel        3037 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
ACPILevel        3038 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
ACPILevel        3039 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
ACPILevel        3040 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
ACPILevel        3041 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
ACPILevel        3042 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
ACPILevel        3043 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
ACPILevel        3044 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
ACPILevel        3045 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
ACPILevel        3046 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
ACPILevel        3047 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
ACPILevel        3049 drivers/gpu/drm/radeon/ci_dpm.c 	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
ACPILevel        3050 drivers/gpu/drm/radeon/ci_dpm.c 	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
ACPILevel         326 drivers/gpu/drm/radeon/smu7_discrete.h     SMU7_Discrete_ACPILevel             ACPILevel;
ACPILevel         234 drivers/gpu/drm/radeon/smu7_fusion.h     SMU7_Fusion_ACPILevel             ACPILevel;