masters            84 drivers/base/component.c static LIST_HEAD(masters);
masters           155 drivers/base/component.c 	list_for_each_entry(m, &masters, node)
masters           274 drivers/base/component.c 	list_for_each_entry(m, &masters, node) {
masters           491 drivers/base/component.c 	list_add(&master->node, &masters);
masters           178 drivers/bus/brcmstb_gisb.c 						u32 masters)
masters           180 drivers/bus/brcmstb_gisb.c 	u32 mask = gdev->valid_mask & masters;
masters            48 drivers/hwtracing/stm/core.c static DEVICE_ATTR_RO(masters);
masters           148 drivers/hwtracing/stm/core.c 	((_s)->masters[(_m) - (_s)->data->sw_start])
masters           193 drivers/hwtracing/stm/policy.c CONFIGFS_ATTR(stp_policy_node_, masters);
masters            45 drivers/hwtracing/stm/stm.h 	struct stp_master	*masters[0];
masters           178 drivers/mfd/qcom-pm8xxx.c 	int	i, ret, masters = 0;
masters           189 drivers/mfd/qcom-pm8xxx.c 	masters = root >> 1;
masters           193 drivers/mfd/qcom-pm8xxx.c 		if (masters & (1 << i))
masters            65 drivers/vme/bridges/vme_fake.c 	struct fake_master_window masters[FAKE_MAX_MASTER];
masters           317 drivers/vme/bridges/vme_fake.c 	bridge->masters[i].enabled = enabled;
masters           318 drivers/vme/bridges/vme_fake.c 	bridge->masters[i].vme_base = vme_base;
masters           319 drivers/vme/bridges/vme_fake.c 	bridge->masters[i].size = size;
masters           320 drivers/vme/bridges/vme_fake.c 	bridge->masters[i].aspace = aspace;
masters           321 drivers/vme/bridges/vme_fake.c 	bridge->masters[i].cycle = cycle;
masters           322 drivers/vme/bridges/vme_fake.c 	bridge->masters[i].dwidth = dwidth;
masters           349 drivers/vme/bridges/vme_fake.c 	*enabled = bridge->masters[i].enabled;
masters           350 drivers/vme/bridges/vme_fake.c 	*vme_base = bridge->masters[i].vme_base;
masters           351 drivers/vme/bridges/vme_fake.c 	*size = bridge->masters[i].size;
masters           352 drivers/vme/bridges/vme_fake.c 	*aspace = bridge->masters[i].aspace;
masters           353 drivers/vme/bridges/vme_fake.c 	*cycle = bridge->masters[i].cycle;
masters           354 drivers/vme/bridges/vme_fake.c 	*dwidth = bridge->masters[i].dwidth;
masters           534 drivers/vme/bridges/vme_fake.c 	addr = (unsigned long long)priv->masters[i].vme_base + offset;
masters           535 drivers/vme/bridges/vme_fake.c 	aspace = priv->masters[i].aspace;
masters           536 drivers/vme/bridges/vme_fake.c 	cycle = priv->masters[i].cycle;
masters           537 drivers/vme/bridges/vme_fake.c 	dwidth = priv->masters[i].dwidth;
masters           727 drivers/vme/bridges/vme_fake.c 	addr = bridge->masters[i].vme_base + offset;
masters           728 drivers/vme/bridges/vme_fake.c 	aspace = bridge->masters[i].aspace;
masters           729 drivers/vme/bridges/vme_fake.c 	cycle = bridge->masters[i].cycle;
masters           730 drivers/vme/bridges/vme_fake.c 	dwidth = bridge->masters[i].dwidth;
masters           824 drivers/vme/bridges/vme_fake.c 	base = bridge->masters[i].vme_base;
masters           825 drivers/vme/bridges/vme_fake.c 	aspace = bridge->masters[i].aspace;
masters           826 drivers/vme/bridges/vme_fake.c 	cycle = bridge->masters[i].cycle;
masters          1262 drivers/vme/bridges/vme_fake.c 		bridge->masters[i].enabled = 0;