masterCmdData1    167 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
masterCmdData1    228 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.u32All = 0;
masterCmdData1    229 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
masterCmdData1    230 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
masterCmdData1    231 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.rfb_update_auto_en =
masterCmdData1    233 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
masterCmdData1    234 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
masterCmdData1    235 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.phy_type  = psr_context->phyType;
masterCmdData1    236 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.frame_cap_ind =
masterCmdData1    238 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_chan = psr_context->channel;
masterCmdData1    239 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
masterCmdData1    241 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 					masterCmdData1.u32All);
masterCmdData1    290 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
masterCmdData1    302 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.u32 = 0;
masterCmdData1    303 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.wait_loop = wait_loop_number;
masterCmdData1    305 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
masterCmdData1    572 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
masterCmdData1    640 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.u32All = 0;
masterCmdData1    641 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
masterCmdData1    642 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
masterCmdData1    643 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.rfb_update_auto_en =
masterCmdData1    645 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
masterCmdData1    646 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
masterCmdData1    647 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.phy_type  = psr_context->phyType;
masterCmdData1    648 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.frame_cap_ind =
masterCmdData1    650 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_chan = psr_context->channel;
masterCmdData1    651 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
masterCmdData1    652 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
masterCmdData1    654 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 					masterCmdData1.u32All);
masterCmdData1    692 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
masterCmdData1    702 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.u32 = 0;
masterCmdData1    703 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.wait_loop = wait_loop_number;
masterCmdData1    705 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);