mast               86 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	u32 mast = nvkm_rd32(device, 0x00c054);
mast               99 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		switch (mast & 0x000c0000) {
mast              109 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		switch (mast & 0x00000003) {
mast              117 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		if ((mast & 0x03000000) != 0x03000000)
mast              120 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		if ((mast & 0x00000200) == 0x00000000)
mast              123 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		switch (mast & 0x00000c00) {
mast              131 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		switch (mast & 0x00000030) {
mast              133 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 			if (mast & 0x00000040)
mast              147 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		switch (mast & 0x00400000) {
mast              160 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
mast              304 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	u32 pllmask = 0, mast;
mast              314 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	mast = nvkm_mask(device, 0xc054, 0x03400e70, 0x03400640);
mast              315 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	mast &= ~0x00400e73;
mast              316 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	mast |= 0x03000000;
mast              321 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		mast |= 0x00000002;
mast              328 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		mast |= 0x00000003;
mast              342 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		mast |= 0x00000020;
mast              349 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		mast |= 0x00000030;
mast              365 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		mast |= 0x00400000;
mast              371 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	nvkm_wr32(device, 0xc054, mast);
mast              102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	u32 mast = nvkm_rd32(device, 0x00c040);
mast              110 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		return read_clk(clk, (mast & 0x00000003) >> 0);
mast              112 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		return read_clk(clk, (mast & 0x00000030) >> 4);
mast              119 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
mast              129 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	u32 src, mast = nvkm_rd32(device, 0x00c040);
mast              133 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		src = !!(mast & 0x00200000);
mast              136 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		src = !!(mast & 0x00400000);
mast              139 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		src = !!(mast & 0x00010000);
mast              142 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		src = !!(mast & 0x02000000);
mast              161 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	u32 mast = nvkm_rd32(device, 0x00c040);
mast              168 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	if (base == 0x004028 && (mast & 0x00100000)) {
mast              197 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	u32 mast = nvkm_rd32(device, 0x00c040);
mast              212 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		switch (mast & 0x30000000) {
mast              220 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		if (!(mast & 0x00100000))
mast              222 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		switch (mast & 0x00000003) {
mast              231 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		switch (mast & 0x00000030) {
mast              233 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 			if (mast & 0x00000080)
mast              244 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 			switch (mast & 0x0000c000) {
mast              264 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 			switch (mast & 0x00000c00) {
mast              272 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 				if (mast & 0x01000000)
mast              280 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 			switch (mast & 0x00000c00) {
mast              305 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 			switch (mast & 0x0c000000) {
mast              320 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
mast              446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, mast, mastm, 0x00000000);
mast              448 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, mast, mastm, mastv);
mast              454 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
mast              456 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
mast              475 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x00100033, 0x00000023);
mast              484 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x00100033, 0x00000033);