masks 36 arch/arm/plat-samsung/include/plat/wakeup-mask.h const struct samsung_wakeup_mask *masks, masks 244 arch/m68k/fpsp040/fpsp.h | FPSR individual bit masks masks 185 arch/mips/kernel/vpe.c static unsigned long const masks[][2] = { masks 199 arch/mips/kernel/vpe.c for (m = 0; m < ARRAY_SIZE(masks); ++m) { masks 203 arch/mips/kernel/vpe.c if ((s->sh_flags & masks[m][0]) != masks[m][0] masks 204 arch/mips/kernel/vpe.c || (s->sh_flags & masks[m][1]) masks 82 arch/powerpc/oprofile/op_model_cell.c unsigned long masks; masks 482 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[next_hdw_thread][i].masks); masks 772 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[0][i].masks = ctr[i].unit_mask; masks 794 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].masks = ctr[i].unit_mask; masks 816 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[0][i].masks); masks 89 arch/powerpc/platforms/ps3/spu.c u64 masks[3]; masks 481 arch/powerpc/platforms/ps3/spu.c spu_pdata(spu)->cache.masks[class] = mask; masks 483 arch/powerpc/platforms/ps3/spu.c spu_pdata(spu)->cache.masks[class]); masks 488 arch/powerpc/platforms/ps3/spu.c return spu_pdata(spu)->cache.masks[class]; masks 720 drivers/acpi/acpi_dbg.c __poll_t masks = 0; masks 724 drivers/acpi/acpi_dbg.c masks |= EPOLLIN | EPOLLRDNORM; masks 726 drivers/acpi/acpi_dbg.c masks |= EPOLLOUT | EPOLLWRNORM; masks 728 drivers/acpi/acpi_dbg.c return masks; masks 104 drivers/char/agp/agp.h const struct gatt_mask *masks; masks 213 drivers/char/agp/ali-agp.c .masks = NULL, masks 237 drivers/char/agp/ali-agp.c .masks = NULL, masks 128 drivers/char/agp/alpha-agp.c .masks = NULL, masks 375 drivers/char/agp/amd-k7-agp.c .masks = amd_irongate_masks, masks 227 drivers/char/agp/amd64-agp.c .masks = NULL, masks 432 drivers/char/agp/ati-agp.c .masks = ati_generic_masks, masks 322 drivers/char/agp/efficeon-agp.c .masks = efficeon_generic_masks, masks 1322 drivers/char/agp/generic.c if (bridge->driver->masks) masks 1323 drivers/char/agp/generic.c return addr | bridge->driver->masks[0].mask; masks 425 drivers/char/agp/hp-agp.c .masks = hp_zx1_masks, masks 552 drivers/char/agp/i460-agp.c return bridge->driver->masks[0].mask masks 566 drivers/char/agp/i460-agp.c .masks = i460_masks, masks 461 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 488 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 515 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 542 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 569 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 596 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 623 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 650 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 677 drivers/char/agp/intel-agp.c .masks = intel_generic_masks, masks 320 drivers/char/agp/nvidia-agp.c .masks = nvidia_generic_masks, masks 220 drivers/char/agp/parisc-agp.c .masks = parisc_agp_masks, masks 133 drivers/char/agp/sis-agp.c .masks = NULL, masks 433 drivers/char/agp/sworks-agp.c .masks = serverworks_masks, masks 520 drivers/char/agp/uninorth-agp.c .masks = NULL, masks 548 drivers/char/agp/uninorth-agp.c .masks = NULL, masks 184 drivers/char/agp/via-agp.c .masks = NULL, masks 211 drivers/char/agp/via-agp.c .masks = NULL, masks 37 drivers/clk/mmp/clk-frac.c (factor->ftbl[i].num * factor->masks->factor)) * 10000; masks 55 drivers/clk/mmp/clk-frac.c struct mmp_clk_factor_masks *masks = factor->masks; masks 61 drivers/clk/mmp/clk-frac.c num = (val >> masks->num_shift) & masks->num_mask; masks 64 drivers/clk/mmp/clk-frac.c den = (val >> masks->den_shift) & masks->den_mask; masks 70 drivers/clk/mmp/clk-frac.c (num * factor->masks->factor)) * 10000; masks 78 drivers/clk/mmp/clk-frac.c struct mmp_clk_factor_masks *masks = factor->masks; masks 86 drivers/clk/mmp/clk-frac.c (factor->ftbl[i].num * factor->masks->factor)) * 10000; masks 98 drivers/clk/mmp/clk-frac.c val &= ~(masks->num_mask << masks->num_shift); masks 99 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; masks 101 drivers/clk/mmp/clk-frac.c val &= ~(masks->den_mask << masks->den_shift); masks 102 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift; masks 115 drivers/clk/mmp/clk-frac.c struct mmp_clk_factor_masks *masks = factor->masks; masks 126 drivers/clk/mmp/clk-frac.c num = (val >> masks->num_shift) & masks->num_mask; masks 129 drivers/clk/mmp/clk-frac.c den = (val >> masks->den_shift) & masks->den_mask; masks 136 drivers/clk/mmp/clk-frac.c val &= ~(masks->num_mask << masks->num_shift); masks 137 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[0].num & masks->num_mask) << masks 138 drivers/clk/mmp/clk-frac.c masks->num_shift; masks 140 drivers/clk/mmp/clk-frac.c val &= ~(masks->den_mask << masks->den_shift); masks 141 drivers/clk/mmp/clk-frac.c val |= (factor->ftbl[0].den & masks->den_mask) << masks 142 drivers/clk/mmp/clk-frac.c masks->den_shift; masks 160 drivers/clk/mmp/clk-frac.c struct mmp_clk_factor_masks *masks, masks 168 drivers/clk/mmp/clk-frac.c if (!masks) { masks 179 drivers/clk/mmp/clk-frac.c factor->masks = masks; masks 29 drivers/clk/mmp/clk.h struct mmp_clk_factor_masks *masks; masks 37 drivers/clk/mmp/clk.h void __iomem *base, struct mmp_clk_factor_masks *masks, masks 80 drivers/clk/spear/clk-aux-synth.c eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; masks 81 drivers/clk/spear/clk-aux-synth.c if (eqn == aux->masks->eq1_mask) masks 85 drivers/clk/spear/clk-aux-synth.c num = (val >> aux->masks->xscale_sel_shift) & masks 86 drivers/clk/spear/clk-aux-synth.c aux->masks->xscale_sel_mask; masks 89 drivers/clk/spear/clk-aux-synth.c den *= (val >> aux->masks->yscale_sel_shift) & masks 90 drivers/clk/spear/clk-aux-synth.c aux->masks->yscale_sel_mask; masks 114 drivers/clk/spear/clk-aux-synth.c ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); masks 115 drivers/clk/spear/clk-aux-synth.c val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << masks 116 drivers/clk/spear/clk-aux-synth.c aux->masks->eq_sel_shift; masks 117 drivers/clk/spear/clk-aux-synth.c val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); masks 118 drivers/clk/spear/clk-aux-synth.c val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) << masks 119 drivers/clk/spear/clk-aux-synth.c aux->masks->xscale_sel_shift; masks 120 drivers/clk/spear/clk-aux-synth.c val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift); masks 121 drivers/clk/spear/clk-aux-synth.c val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) << masks 122 drivers/clk/spear/clk-aux-synth.c aux->masks->yscale_sel_shift; masks 139 drivers/clk/spear/clk-aux-synth.c const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, masks 156 drivers/clk/spear/clk-aux-synth.c if (!masks) masks 157 drivers/clk/spear/clk-aux-synth.c aux->masks = &default_aux_masks; masks 159 drivers/clk/spear/clk-aux-synth.c aux->masks = masks; masks 182 drivers/clk/spear/clk-aux-synth.c aux->masks->enable_bit, 0, lock); masks 52 drivers/clk/spear/clk.h const struct aux_clk_masks *masks; masks 115 drivers/clk/spear/clk.h const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, masks 39 drivers/clk/uniphier/clk-uniphier-mio.c .masks = { \ masks 17 drivers/clk/uniphier/clk-uniphier-mux.c const unsigned int *masks; masks 27 drivers/clk/uniphier/clk-uniphier-mux.c return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], masks 44 drivers/clk/uniphier/clk-uniphier-mux.c if ((mux->masks[i] & val) == mux->vals[i]) masks 77 drivers/clk/uniphier/clk-uniphier-mux.c mux->masks = data->masks; masks 52 drivers/clk/uniphier/clk-uniphier.h unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS]; masks 449 drivers/crypto/hifn_795x.c volatile __le16 masks; masks 471 drivers/crypto/hifn_795x.c volatile __le16 masks; masks 501 drivers/crypto/hifn_795x.c volatile __le16 masks; masks 529 drivers/crypto/hifn_795x.c volatile __le16 masks; masks 1055 drivers/crypto/hifn_795x.c base_cmd->masks = __cpu_to_le16(mask); masks 1083 drivers/crypto/hifn_795x.c cry_cmd->masks = __cpu_to_le16(mode | masks 46 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c aud->shifts->field_name, aud->masks->field_name masks 940 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c const struct dce_audio_mask *masks masks 956 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c audio->masks = masks; masks 128 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h const struct dce_audio_mask *masks; masks 136 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h const struct dce_audio_mask *masks); masks 38 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c hws->shifts->field_name, hws->masks->field_name masks 75 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) masks 120 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (hws->masks->BLND_ALPHA_MODE != 0) { masks 41 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name masks 80 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) masks 82 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) masks 84 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) masks 86 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) masks 283 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) masks 621 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_mask *masks) masks 628 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->masks = masks; masks 645 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_mask *masks) masks 655 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c masks); masks 680 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_mask *masks) masks 687 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c masks); masks 697 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_mask *masks) masks 704 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c masks); masks 715 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_mask *masks) masks 722 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c masks); masks 280 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_mask *masks; masks 289 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_mask *masks); masks 297 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_mask *masks); masks 305 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_mask *masks); masks 313 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_mask *masks); masks 322 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_mask *masks); masks 37 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->shifts->field_name, dce_mi->masks->field_name masks 358 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ masks 372 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ masks 783 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->masks = mi_mask; masks 335 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h const struct dce_mem_input_mask *masks; masks 474 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c hws->masks = &hwseq_mask; masks 83 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c hws->shifts->field_name, hws->masks->field_name masks 521 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c hws->masks = &hwseq_mask; masks 494 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c hws->masks = &hwseq_mask; masks 47 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c hws->shifts->field_name, hws->masks->field_name masks 741 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c hws->masks = &hwseq_mask; masks 755 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c hws->masks = &dce121_hwseq_mask; masks 586 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c hws->masks = &hwseq_mask; masks 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c reg->shifts.field_name, reg->masks.field_name masks 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h struct xfer_func_mask masks; masks 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h struct cm_color_matrix_mask masks; masks 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; masks 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; masks 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; masks 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; masks 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; masks 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; masks 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; masks 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; masks 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; masks 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; masks 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; masks 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; masks 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; masks 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; masks 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; masks 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; masks 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; masks 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; masks 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; masks 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; masks 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B; masks 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; masks 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B; masks 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; masks 488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; masks 490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; masks 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name masks 966 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->masks = hubbub_mask; masks 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h const struct dcn_hubbub_mask *masks; masks 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hws->shifts->field_name, hws->masks->field_name masks 846 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c hws->masks = &hwseq_mask; masks 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; masks 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; masks 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; masks 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; masks 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; masks 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; masks 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; masks 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; masks 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; masks 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; masks 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name masks 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name masks 618 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->masks = hubbub_mask; masks 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h const struct dcn_hubbub_mask *masks; masks 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hws->shifts->field_name, hws->masks->field_name masks 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; masks 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; masks 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; masks 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; masks 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; masks 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; masks 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; masks 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; masks 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; masks 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; masks 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; masks 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; masks 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; masks 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; masks 1112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vmid->masks = &vmid_masks; masks 1254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c hws->masks = &hwseq_mask; masks 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c vmid->shifts->field_name, vmid->masks->field_name masks 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h const struct dcn20_vmid_mask *masks; masks 40 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name masks 50 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name masks 602 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->masks = hubbub_mask; masks 1186 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vmid->masks = &vmid_masks; masks 1404 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c hws->masks = &hwseq_mask; masks 137 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->masks = &ddc_mask; masks 147 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c hpd->masks = &hpd_mask; masks 150 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->masks = &ddc_mask; masks 160 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c hpd->masks = &hpd_mask; masks 137 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->masks = &ddc_mask; masks 147 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c hpd->masks = &hpd_mask; masks 157 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c generic->masks = &generic_mask[en]; masks 182 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->masks = &ddc_mask; masks 192 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c hpd->masks = &hpd_mask; masks 189 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->masks = &ddc_mask[en]; masks 199 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c hpd->masks = &hpd_mask; masks 209 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c generic->masks = &generic_mask[en]; masks 166 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c generic->masks = &generic_mask[en]; masks 191 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->masks = &ddc_mask[en]; masks 201 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c hpd->masks = &hpd_mask; masks 42 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->shifts->field_name, ddc->masks->field_name masks 35 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h const struct ddc_sh_mask *masks; masks 40 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c generic->shifts->field_name, generic->masks->field_name masks 36 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h const struct generic_sh_mask *masks; masks 40 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c hpd->shifts->field_name, hpd->masks->field_name masks 35 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h const struct hpd_sh_mask *masks; masks 62 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h const struct dce_hwseq_mask *masks; masks 211 drivers/gpu/drm/via/via_irq.c maskarray_t *masks; masks 234 drivers/gpu/drm/via/via_irq.c masks = dev_priv->irq_masks; masks 237 drivers/gpu/drm/via/via_irq.c if (masks[real_irq][2] && !force_sequence) { masks 239 drivers/gpu/drm/via/via_irq.c ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == masks 240 drivers/gpu/drm/via/via_irq.c masks[irq][4])); masks 1449 drivers/iio/adc/max1363.c unsigned long *masks; masks 1452 drivers/iio/adc/max1363.c masks = devm_kzalloc(&indio_dev->dev, masks 1457 drivers/iio/adc/max1363.c if (!masks) masks 1461 drivers/iio/adc/max1363.c bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i, masks 1465 drivers/iio/adc/max1363.c indio_dev->available_scan_masks = masks; masks 3185 drivers/media/pci/bt8xx/bttv-cards.c static const int masks[] = {0x30, 0x01, 0x12, 0x23}; masks 3186 drivers/media/pci/bt8xx/bttv-cards.c gpio_write(masks[input%4]); masks 4571 drivers/media/pci/bt8xx/bttv-cards.c static const int masks[] = { masks 4577 drivers/media/pci/bt8xx/bttv-cards.c gpio_write(masks[input%16]); masks 241 drivers/media/usb/cpia2/cpia2.h struct cpia2_reg_mask masks[16]; masks 466 drivers/net/ethernet/freescale/dpaa2/dpkg.h struct dpkg_mask masks[DPKG_NUM_OF_MASKS]; masks 422 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h struct dpni_mask_cfg masks[4]; masks 66 drivers/net/ethernet/freescale/dpaa2/dpni.c extr->masks[j].mask = cfg->extracts[i].masks[j].mask; masks 67 drivers/net/ethernet/freescale/dpaa2/dpni.c extr->masks[j].offset = masks 68 drivers/net/ethernet/freescale/dpaa2/dpni.c cfg->extracts[i].masks[j].offset; masks 2211 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c struct pedit_headers masks; masks 2230 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset); masks 2352 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c set_masks = &hdrs[0].masks; masks 2353 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c add_masks = &hdrs[1].masks; masks 2564 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c cmd_masks = &hdrs[cmd].masks; masks 1420 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c } __aligned(BITS_PER_LONG / 8) masks; masks 1468 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c rule->match.mask = (void *)&masks; masks 1473 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c masks.mask.src = src_mask; masks 1474 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c masks.mask.dst = dst_mask; masks 560 drivers/pci/msi.c struct irq_affinity_desc *masks = NULL; masks 565 drivers/pci/msi.c masks = irq_create_affinity_masks(nvec, affd); masks 568 drivers/pci/msi.c entry = alloc_msi_entry(&dev->dev, nvec, masks); masks 593 drivers/pci/msi.c kfree(masks); masks 698 drivers/pci/msi.c struct irq_affinity_desc *curmsk, *masks = NULL; masks 704 drivers/pci/msi.c masks = irq_create_affinity_masks(nvec, affd); masks 706 drivers/pci/msi.c for (i = 0, curmsk = masks; i < nvec; i++) { masks 732 drivers/pci/msi.c if (masks) masks 737 drivers/pci/msi.c kfree(masks); masks 621 drivers/s390/char/sclp.c u8 masks[2 * 1021 + 4]; /* variable length */ masks 106 drivers/s390/char/sclp.h u8 masks[4 * 1021]; /* variable length */ masks 117 drivers/s390/char/sclp.h static inline sccb_mask_t sccb_get_mask(u8 *masks, size_t len, int i) masks 121 drivers/s390/char/sclp.h memcpy(&res, masks + i * len, min(sizeof(res), len)); masks 125 drivers/s390/char/sclp.h static inline void sccb_set_mask(u8 *masks, size_t len, int i, sccb_mask_t val) masks 127 drivers/s390/char/sclp.h memset(masks + i * len, 0, len); masks 128 drivers/s390/char/sclp.h memcpy(masks + i * len, &val, min(sizeof(val), len)); masks 135 drivers/s390/char/sclp.h sccb_get_mask(__sccb->masks, __sccb->mask_length, i); \ masks 146 drivers/s390/char/sclp.h sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \ masks 468 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c symlist_t masks; masks 485 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c SLIST_INIT(&masks); masks 505 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c symlist_add(&masks, cursym, SYMLIST_SORT); masks 576 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c while (SLIST_FIRST(&masks) != NULL) { masks 579 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c curnode = SLIST_FIRST(&masks); masks 580 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c SLIST_REMOVE_HEAD(&masks, links); masks 18 drivers/staging/speakup/keyhelp.c static u_short masks[] = { 32, 16, 8, 4, 2, 1 }; masks 106 drivers/staging/speakup/keyhelp.c if (state & masks[i]) masks 237 include/sound/pcm.h struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - masks 249 include/sound/pcm.h return &constrs->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; masks 883 include/sound/pcm.h return ¶ms->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; masks 895 include/sound/pcm.h return ¶ms->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; masks 398 include/uapi/sound/asound.h struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - masks 45 kernel/irq/affinity.c cpumask_var_t *masks; masks 48 kernel/irq/affinity.c masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL); masks 49 kernel/irq/affinity.c if (!masks) masks 53 kernel/irq/affinity.c if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL)) masks 57 kernel/irq/affinity.c return masks; masks 61 kernel/irq/affinity.c free_cpumask_var(masks[node]); masks 62 kernel/irq/affinity.c kfree(masks); masks 66 kernel/irq/affinity.c static void free_node_to_cpumask(cpumask_var_t *masks) masks 71 kernel/irq/affinity.c free_cpumask_var(masks[node]); masks 72 kernel/irq/affinity.c kfree(masks); masks 75 kernel/irq/affinity.c static void build_node_to_cpumask(cpumask_var_t *masks) masks 80 kernel/irq/affinity.c cpumask_set_cpu(cpu, masks[cpu_to_node(cpu)]); masks 253 kernel/irq/affinity.c struct irq_affinity_desc *masks) masks 272 kernel/irq/affinity.c cpumask_or(&masks[curvec].mask, &masks[curvec].mask, masks 324 kernel/irq/affinity.c irq_spread_init_one(&masks[curvec].mask, nmsk, masks 340 kernel/irq/affinity.c struct irq_affinity_desc *masks) masks 364 kernel/irq/affinity.c nmsk, masks); masks 382 kernel/irq/affinity.c masks); masks 419 kernel/irq/affinity.c struct irq_affinity_desc *masks = NULL; masks 449 kernel/irq/affinity.c masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL); masks 450 kernel/irq/affinity.c if (!masks) masks 455 kernel/irq/affinity.c cpumask_copy(&masks[curvec].mask, irq_default_affinity); masks 466 kernel/irq/affinity.c curvec, masks); masks 468 kernel/irq/affinity.c kfree(masks); masks 481 kernel/irq/affinity.c cpumask_copy(&masks[curvec].mask, irq_default_affinity); masks 485 kernel/irq/affinity.c masks[i].is_managed = 1; masks 487 kernel/irq/affinity.c return masks; masks 2422 kernel/module.c static unsigned long const masks[][2] = { masks 2438 kernel/module.c for (m = 0; m < ARRAY_SIZE(masks); ++m) { masks 2443 kernel/module.c if ((s->sh_flags & masks[m][0]) != masks[m][0] masks 2444 kernel/module.c || (s->sh_flags & masks[m][1]) masks 2471 kernel/module.c for (m = 0; m < ARRAY_SIZE(masks); ++m) { masks 2476 kernel/module.c if ((s->sh_flags & masks[m][0]) != masks[m][0] masks 2477 kernel/module.c || (s->sh_flags & masks[m][1]) masks 890 net/core/filter.c u16 *masks, memvalid = 0; /* One bit per cell, 16 cells */ masks 895 net/core/filter.c masks = kmalloc_array(flen, sizeof(*masks), GFP_KERNEL); masks 896 net/core/filter.c if (!masks) masks 899 net/core/filter.c memset(masks, 0xff, flen * sizeof(*masks)); masks 902 net/core/filter.c memvalid &= masks[pc]; masks 918 net/core/filter.c masks[pc + 1 + filter[pc].k] &= memvalid; masks 930 net/core/filter.c masks[pc + 1 + filter[pc].jt] &= memvalid; masks 931 net/core/filter.c masks[pc + 1 + filter[pc].jf] &= memvalid; masks 937 net/core/filter.c kfree(masks); masks 74 net/netlink/af_netlink.c unsigned long masks[0]; masks 551 net/netlink/af_netlink.c listeners->masks[i] = mask; masks 1359 net/netlink/af_netlink.c res = test_bit(group - 1, listeners->masks); masks 2123 net/netlink/af_netlink.c memcpy(new->masks, old->masks, NLGRPSZ(tbl->groups)); masks 96 net/sched/cls_flower.c struct list_head masks; masks 305 net/sched/cls_flower.c list_for_each_entry_rcu(mask, &head->masks, list) { masks 340 net/sched/cls_flower.c INIT_LIST_HEAD_RCU(&head->masks); masks 570 net/sched/cls_flower.c list_for_each_entry_safe(mask, next_mask, &head->masks, list) { masks 1405 net/sched/cls_flower.c list_add_tail_rcu(&newmask->list, &head->masks); masks 1729 net/sched/cls_flower.c *last = list_empty(&head->masks); masks 1145 security/smack/smackfs.c unsigned int masks; masks 1176 security/smack/smackfs.c &host[0], &host[1], &host[2], &host[3], &masks, smack); masks 1185 security/smack/smackfs.c masks = 32; masks 1187 security/smack/smackfs.c if (masks > BEBITS) { masks 1211 security/smack/smackfs.c for (m = masks, temp_mask = 0; m > 0; m--) { masks 1228 security/smack/smackfs.c if (snp->smk_host.s_addr == nsa && snp->smk_masks == masks) { masks 1244 security/smack/smackfs.c snp->smk_masks = masks; masks 56 sound/core/pcm_compat.c struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; /* this must be identical */ masks 44 sound/core/pcm_native.c unsigned int masks[SNDRV_PCM_HW_PARAM_SUBFORMAT - masks 3577 sound/core/pcm_native.c for (i = 0; i < ARRAY_SIZE(oparams->masks); i++) masks 3578 sound/core/pcm_native.c params->masks[i].bits[0] = oparams->masks[i]; masks 3596 sound/core/pcm_native.c for (i = 0; i < ARRAY_SIZE(oparams->masks); i++) masks 3597 sound/core/pcm_native.c oparams->masks[i] = params->masks[i].bits[0]; masks 1322 sound/soc/codecs/cs35l36.c unsigned int masks[4]; masks 1329 sound/soc/codecs/cs35l36.c regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks, masks 1330 sound/soc/codecs/cs35l36.c ARRAY_SIZE(masks)); masks 1333 sound/soc/codecs/cs35l36.c if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && masks 1334 sound/soc/codecs/cs35l36.c !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) { masks 1339 sound/soc/codecs/cs42l42.c unsigned int masks[12]; masks 1349 sound/soc/codecs/cs42l42.c &(masks[i])); masks 1350 sound/soc/codecs/cs42l42.c stickies[i] = stickies[i] & (~masks[i]) & masks 1366 sound/soc/codecs/cs42l42.c if ((~masks[5]) & irq_params_table[5].mask) { masks 1376 sound/soc/codecs/cs42l42.c if ((~masks[11]) & irq_params_table[11].mask) { masks 1401 sound/soc/codecs/cs42l42.c if ((~masks[7]) & irq_params_table[7].mask) { masks 2164 sound/soc/codecs/cs43130.c unsigned int masks[CS43130_NUM_INT]; masks 2171 sound/soc/codecs/cs43130.c &masks[i]); masks 2175 sound/soc/codecs/cs43130.c stickies[i] = stickies[i] & (~masks[i]); masks 398 tools/include/uapi/sound/asound.h struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - masks 64 tools/perf/trace/beauty/prctl.c const u8 masks[] = { masks 77 tools/perf/trace/beauty/prctl.c if (option < ARRAY_SIZE(masks)) masks 78 tools/perf/trace/beauty/prctl.c arg->mask |= masks[option];