mask_sh 89 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ mask_sh 90 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \ mask_sh 92 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \ mask_sh 93 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \ mask_sh 95 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \ mask_sh 96 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \ mask_sh 97 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ mask_sh 102 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) mask_sh 104 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ mask_sh 105 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 107 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ mask_sh 109 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_VMAX_SEL, mask_sh), \ mask_sh 111 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ mask_sh 113 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ mask_sh 115 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ mask_sh 117 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ mask_sh 123 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h BL1_PWM_USER_LEVEL, mask_sh), \ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) mask_sh 135 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 138 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_VMAX_SEL, mask_sh), \ mask_sh 142 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ mask_sh 144 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ mask_sh 146 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ mask_sh 148 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ mask_sh 150 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ mask_sh 152 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ mask_sh 154 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h BL1_PWM_USER_LEVEL, mask_sh), \ mask_sh 156 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ mask_sh 158 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ mask_sh 160 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ mask_sh 162 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ mask_sh 164 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) mask_sh 167 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) mask_sh 48 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h #define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\ mask_sh 49 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ mask_sh 51 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\ mask_sh 53 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ mask_sh 56 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ mask_sh 57 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\ mask_sh 58 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\ mask_sh 59 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\ mask_sh 60 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) mask_sh 62 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h #define AUD_COMMON_MASK_SH_LIST(mask_sh)\ mask_sh 63 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h AUD_COMMON_MASK_SH_LIST_BASE(mask_sh),\ mask_sh 64 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ mask_sh 65 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh) mask_sh 48 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ mask_sh 49 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ mask_sh 51 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) mask_sh 54 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ mask_sh 56 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) mask_sh 99 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ mask_sh 100 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ mask_sh 101 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ mask_sh 102 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ mask_sh 103 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) mask_sh 123 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) mask_sh 77 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_ENABLE, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h UC_IN_STOP_MODE, mask_sh), \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h UC_IN_RESET, mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h IRAM_HOST_ACCESS_EN, mask_sh), \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h IRAM_WR_ADDR_AUTO_INC, mask_sh), \ mask_sh 89 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h IRAM_RD_ADDR_AUTO_INC, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ mask_sh 92 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \ mask_sh 96 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) mask_sh 103 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \ mask_sh 105 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_ENABLE, mask_sh), \ mask_sh 107 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h UC_IN_STOP_MODE, mask_sh), \ mask_sh 109 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h UC_IN_RESET, mask_sh), \ mask_sh 111 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h IRAM_HOST_ACCESS_EN, mask_sh), \ mask_sh 113 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h IRAM_WR_ADDR_AUTO_INC, mask_sh), \ mask_sh 115 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h IRAM_RD_ADDR_AUTO_INC, mask_sh), \ mask_sh 117 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ mask_sh 118 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \ mask_sh 122 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_IRAM_MEM_PWR_STATE, mask_sh) mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_IRAM_MEM_PWR_STATE, mask_sh) mask_sh 449 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ mask_sh 450 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ mask_sh 451 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) mask_sh 453 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ mask_sh 454 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ mask_sh 455 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ mask_sh 456 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ mask_sh 457 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ mask_sh 458 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ mask_sh 459 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ mask_sh 460 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ mask_sh 461 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ mask_sh 462 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) mask_sh 464 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ mask_sh 465 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ mask_sh 466 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) mask_sh 468 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ mask_sh 469 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ mask_sh 470 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) mask_sh 472 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\ mask_sh 473 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ mask_sh 474 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ mask_sh 475 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ mask_sh 476 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) mask_sh 478 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ mask_sh 479 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ mask_sh 480 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ mask_sh 481 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ mask_sh 482 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ mask_sh 483 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ mask_sh 484 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ mask_sh 485 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) mask_sh 487 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ mask_sh 488 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ mask_sh 489 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ mask_sh 490 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ mask_sh 491 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) mask_sh 493 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ mask_sh 494 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ mask_sh 495 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ mask_sh 496 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) mask_sh 498 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ mask_sh 499 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ mask_sh 500 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) mask_sh 502 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ mask_sh 503 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ mask_sh 504 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ mask_sh 505 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ mask_sh 506 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ mask_sh 507 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) mask_sh 509 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ mask_sh 510 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ mask_sh 511 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ mask_sh 512 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ mask_sh 513 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ mask_sh 514 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\ mask_sh 515 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) mask_sh 517 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ mask_sh 518 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ mask_sh 519 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ mask_sh 520 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) mask_sh 522 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ mask_sh 523 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ mask_sh 524 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ mask_sh 525 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ mask_sh 526 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ mask_sh 527 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) mask_sh 529 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ mask_sh 530 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ mask_sh 531 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ mask_sh 532 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ mask_sh 533 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ mask_sh 534 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ mask_sh 535 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ mask_sh 536 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ mask_sh 538 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ mask_sh 539 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ mask_sh 540 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ mask_sh 541 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ mask_sh 542 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ mask_sh 543 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ mask_sh 544 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ mask_sh 545 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ mask_sh 546 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ mask_sh 547 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ mask_sh 548 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ mask_sh 549 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ mask_sh 550 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ mask_sh 551 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ mask_sh 552 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ mask_sh 553 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ mask_sh 554 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ mask_sh 555 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ mask_sh 556 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ mask_sh 557 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ mask_sh 558 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ mask_sh 559 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ mask_sh 560 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ mask_sh 561 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ mask_sh 562 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ mask_sh 563 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 564 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 565 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 566 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 567 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 568 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 569 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 570 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 571 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ mask_sh 572 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ mask_sh 573 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ mask_sh 574 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ mask_sh 575 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ mask_sh 576 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ mask_sh 577 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ mask_sh 578 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) mask_sh 581 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ mask_sh 582 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ mask_sh 583 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ mask_sh 584 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ mask_sh 585 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ mask_sh 586 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ mask_sh 587 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ mask_sh 588 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ mask_sh 589 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ mask_sh 590 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ mask_sh 591 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ mask_sh 592 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ mask_sh 593 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ mask_sh 594 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ mask_sh 595 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ mask_sh 596 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ mask_sh 597 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ mask_sh 598 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ mask_sh 599 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ mask_sh 600 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ mask_sh 601 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ mask_sh 602 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ mask_sh 603 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ mask_sh 604 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ mask_sh 605 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ mask_sh 606 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ mask_sh 607 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ mask_sh 608 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ mask_sh 609 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ mask_sh 610 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ mask_sh 611 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ mask_sh 612 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ mask_sh 613 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ mask_sh 614 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ mask_sh 615 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ mask_sh 616 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ mask_sh 617 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ mask_sh 618 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ mask_sh 619 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ mask_sh 620 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 621 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 622 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 623 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 624 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 625 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 626 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 627 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 628 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 629 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 630 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 631 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 632 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 633 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 634 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 635 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 636 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 637 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 638 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ mask_sh 639 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_LVTMA_MASK_SH_LIST(mask_sh) mask_sh 643 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ mask_sh 644 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ mask_sh 645 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ mask_sh 646 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ mask_sh 647 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ mask_sh 648 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ mask_sh 649 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ mask_sh 650 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ mask_sh 651 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ mask_sh 652 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ mask_sh 653 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ mask_sh 654 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ mask_sh 655 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ mask_sh 656 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ mask_sh 657 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ mask_sh 658 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ mask_sh 659 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ mask_sh 660 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ mask_sh 661 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ mask_sh 662 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ mask_sh 663 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ mask_sh 664 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ mask_sh 665 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ mask_sh 666 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ mask_sh 667 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ mask_sh 668 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ mask_sh 669 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ mask_sh 670 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 671 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 672 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 673 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 674 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 675 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 676 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 677 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 678 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 679 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 680 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ mask_sh 681 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ mask_sh 682 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ mask_sh 683 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) mask_sh 101 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h #define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ mask_sh 102 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ mask_sh 103 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\ mask_sh 104 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\ mask_sh 105 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\ mask_sh 106 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\ mask_sh 107 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\ mask_sh 108 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\ mask_sh 109 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_HW_STATUS, DC_I2C_DDC1_HW_STATUS, mask_sh),\ mask_sh 110 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, mask_sh),\ mask_sh 111 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\ mask_sh 112 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\ mask_sh 113 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\ mask_sh 114 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\ mask_sh 115 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\ mask_sh 116 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\ mask_sh 117 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\ mask_sh 118 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\ mask_sh 123 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\ mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\ mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh) mask_sh 139 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh) mask_sh 230 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh) mask_sh 67 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h #define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ mask_sh 68 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ mask_sh 69 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ mask_sh 70 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 71 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 72 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ mask_sh 73 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 74 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 75 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 76 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 77 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ mask_sh 78 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ mask_sh 82 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 84 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 86 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ mask_sh 88 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ mask_sh 89 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ mask_sh 90 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ mask_sh 92 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ mask_sh 93 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ mask_sh 95 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 96 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ mask_sh 97 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ mask_sh 102 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ mask_sh 103 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ mask_sh 104 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) mask_sh 106 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h #define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ mask_sh 107 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 108 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh) mask_sh 110 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h #define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \ mask_sh 111 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ mask_sh 112 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ mask_sh 113 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 114 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 115 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ mask_sh 116 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 117 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 118 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 120 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ mask_sh 122 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ mask_sh 123 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 128 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 130 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ mask_sh 132 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ mask_sh 134 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ mask_sh 135 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ mask_sh 137 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ mask_sh 138 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ mask_sh 139 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ mask_sh 141 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ mask_sh 142 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ mask_sh 143 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ mask_sh 144 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ mask_sh 145 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ mask_sh 146 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ mask_sh 147 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ mask_sh 148 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCP_MASK_SH_LIST(mask_sh, blk)\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh) mask_sh 165 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh) mask_sh 168 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh) mask_sh 175 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ mask_sh 176 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\ mask_sh 177 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ mask_sh 180 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh) mask_sh 186 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh) mask_sh 194 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCE8_MASK_SH_LIST(mask_sh)\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCP_MASK_SH_LIST(mask_sh, ),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_GFX8_TILE_MASK_SH_LIST(mask_sh, ) mask_sh 200 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCE11_2_MASK_SH_LIST(mask_sh)\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCE8_MASK_SH_LIST(mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCP_DCE11_MASK_SH_LIST(mask_sh, ) mask_sh 204 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCE11_MASK_SH_LIST(mask_sh)\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCE11_2_MASK_SH_LIST(mask_sh),\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) mask_sh 208 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) mask_sh 215 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) mask_sh 228 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ mask_sh 229 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ mask_sh 230 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ mask_sh 233 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) mask_sh 235 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define MI_DCE12_MASK_SH_LIST(mask_sh)\ mask_sh 236 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ mask_sh 237 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh) mask_sh 87 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ mask_sh 88 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ mask_sh 89 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ mask_sh 90 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ mask_sh 91 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ mask_sh 92 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ mask_sh 93 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ mask_sh 94 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ mask_sh 95 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ mask_sh 96 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ mask_sh 97 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ mask_sh 98 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ mask_sh 99 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ mask_sh 100 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ mask_sh 101 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ mask_sh 102 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ mask_sh 103 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ mask_sh 104 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ mask_sh 105 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ mask_sh 106 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ mask_sh 107 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ mask_sh 108 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ mask_sh 109 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ mask_sh 110 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ mask_sh 111 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ mask_sh 112 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ mask_sh 113 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ mask_sh 114 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ mask_sh 115 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ mask_sh 116 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ mask_sh 117 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ mask_sh 118 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) mask_sh 130 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) mask_sh 147 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) mask_sh 150 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ mask_sh 164 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ mask_sh 165 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ mask_sh 167 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ mask_sh 168 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ mask_sh 174 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ mask_sh 175 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ mask_sh 176 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ mask_sh 177 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ mask_sh 180 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) mask_sh 118 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ mask_sh 123 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ mask_sh 164 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ mask_sh 165 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_N, DP_VID_N, mask_sh),\ mask_sh 167 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_M, DP_VID_M, mask_sh),\ mask_sh 168 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ mask_sh 174 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ mask_sh 175 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ mask_sh 176 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ mask_sh 177 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ mask_sh 180 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ mask_sh 194 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ mask_sh 199 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ mask_sh 200 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh) mask_sh 205 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) mask_sh 208 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ mask_sh 214 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ mask_sh 215 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ mask_sh 227 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ mask_sh 228 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ mask_sh 229 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ mask_sh 230 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ mask_sh 233 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ mask_sh 234 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ mask_sh 235 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ mask_sh 236 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ mask_sh 237 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ mask_sh 253 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ mask_sh 254 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ mask_sh 255 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ mask_sh 256 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ mask_sh 257 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ mask_sh 258 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ mask_sh 259 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ mask_sh 260 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ mask_sh 261 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ mask_sh 262 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ mask_sh 263 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ mask_sh 264 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ mask_sh 265 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ mask_sh 266 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ mask_sh 267 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ mask_sh 268 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ mask_sh 269 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ mask_sh 270 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ mask_sh 271 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ mask_sh 272 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ mask_sh 273 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ mask_sh 274 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ mask_sh 275 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ mask_sh 276 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ mask_sh 277 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ mask_sh 278 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ mask_sh 279 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ mask_sh 280 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ mask_sh 281 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ mask_sh 282 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ mask_sh 283 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ mask_sh 284 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ mask_sh 285 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ mask_sh 286 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ mask_sh 287 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ mask_sh 288 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ mask_sh 289 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh) mask_sh 291 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ mask_sh 292 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) mask_sh 294 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ mask_sh 295 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ mask_sh 296 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ mask_sh 297 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh) mask_sh 299 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ mask_sh 300 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ mask_sh 301 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ mask_sh 302 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ mask_sh 303 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ mask_sh 304 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ mask_sh 305 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ mask_sh 306 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ mask_sh 307 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh) mask_sh 309 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\ mask_sh 310 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ mask_sh 311 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ mask_sh 312 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ mask_sh 313 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ mask_sh 314 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ mask_sh 315 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ mask_sh 316 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) mask_sh 318 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\ mask_sh 319 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ mask_sh 320 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ mask_sh 321 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\ mask_sh 322 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\ mask_sh 323 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\ mask_sh 324 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\ mask_sh 325 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\ mask_sh 326 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\ mask_sh 327 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ mask_sh 328 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ mask_sh 329 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) mask_sh 331 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ mask_sh 332 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ mask_sh 333 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ mask_sh 334 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ mask_sh 335 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ mask_sh 336 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 337 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 338 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 339 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 340 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 341 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 342 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 343 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 344 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\ mask_sh 345 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\ mask_sh 346 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ mask_sh 347 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ mask_sh 348 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ mask_sh 349 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ mask_sh 350 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ mask_sh 351 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ mask_sh 352 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ mask_sh 353 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ mask_sh 354 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ mask_sh 355 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ mask_sh 356 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ mask_sh 357 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ mask_sh 358 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ mask_sh 359 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ mask_sh 360 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ mask_sh 361 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ mask_sh 362 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ mask_sh 363 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ mask_sh 364 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ mask_sh 365 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ mask_sh 366 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ mask_sh 367 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ mask_sh 368 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ mask_sh 369 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh) mask_sh 114 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h #define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ mask_sh 115 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ mask_sh 116 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ mask_sh 117 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ mask_sh 118 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ mask_sh 119 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ mask_sh 120 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ mask_sh 121 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ mask_sh 122 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ mask_sh 123 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ mask_sh 124 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ mask_sh 125 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ mask_sh 126 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ mask_sh 127 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ mask_sh 128 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \ mask_sh 129 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ mask_sh 130 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ mask_sh 131 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ mask_sh 132 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ mask_sh 133 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ mask_sh 134 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ mask_sh 135 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ mask_sh 136 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ mask_sh 137 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ mask_sh 138 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ mask_sh 139 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ mask_sh 140 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ mask_sh 141 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ mask_sh 142 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ mask_sh 143 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ mask_sh 144 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \ mask_sh 160 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ mask_sh 161 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ mask_sh 162 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ mask_sh 163 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ mask_sh 164 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ mask_sh 165 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ mask_sh 166 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ mask_sh 167 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ mask_sh 168 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ mask_sh 169 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ mask_sh 170 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ mask_sh 171 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ mask_sh 172 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ mask_sh 173 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ mask_sh 174 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ mask_sh 175 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ mask_sh 176 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ mask_sh 177 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ mask_sh 178 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ mask_sh 179 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ mask_sh 180 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ mask_sh 181 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ mask_sh 182 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ mask_sh 183 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ mask_sh 184 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ mask_sh 185 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ mask_sh 186 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ mask_sh 187 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ mask_sh 188 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ mask_sh 189 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ mask_sh 190 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh) mask_sh 192 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \ mask_sh 193 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 194 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) mask_sh 198 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h #define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \ mask_sh 199 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ mask_sh 200 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ mask_sh 201 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ mask_sh 202 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ mask_sh 204 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) mask_sh 207 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ mask_sh 208 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ mask_sh 209 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ mask_sh 210 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ mask_sh 211 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ mask_sh 212 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ mask_sh 213 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ mask_sh 214 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ mask_sh 215 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ mask_sh 216 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ mask_sh 217 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ mask_sh 218 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ mask_sh 219 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ mask_sh 220 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ mask_sh 221 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ mask_sh 222 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ mask_sh 223 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ mask_sh 224 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ mask_sh 225 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ mask_sh 226 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ mask_sh 227 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ mask_sh 228 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ mask_sh 229 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ mask_sh 230 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ mask_sh 231 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ mask_sh 232 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ mask_sh 233 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ mask_sh 234 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ mask_sh 235 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ mask_sh 236 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ mask_sh 237 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ mask_sh 253 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ mask_sh 254 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ mask_sh 255 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ mask_sh 256 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ mask_sh 257 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ mask_sh 258 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ mask_sh 259 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ mask_sh 260 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ mask_sh 261 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ mask_sh 262 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ mask_sh 263 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ mask_sh 264 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ mask_sh 265 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ mask_sh 266 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ mask_sh 267 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ mask_sh 268 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ mask_sh 269 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ mask_sh 270 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ mask_sh 271 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ mask_sh 272 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ mask_sh 273 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ mask_sh 274 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ mask_sh 275 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ mask_sh 276 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ mask_sh 277 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ mask_sh 278 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ mask_sh 279 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ mask_sh 280 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ mask_sh 281 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ mask_sh 282 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ mask_sh 283 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ mask_sh 284 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ mask_sh 285 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ mask_sh 286 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ mask_sh 287 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ mask_sh 288 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) mask_sh 346 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ mask_sh 347 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ mask_sh 348 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ mask_sh 349 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ mask_sh 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ mask_sh 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ mask_sh 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ mask_sh 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\ mask_sh 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\ mask_sh 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\ mask_sh 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\ mask_sh 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ mask_sh 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ mask_sh 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \ mask_sh 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ mask_sh 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \ mask_sh 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ mask_sh 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \ mask_sh 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ mask_sh 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ mask_sh 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ mask_sh 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ mask_sh 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ mask_sh 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \ mask_sh 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \ mask_sh 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \ mask_sh 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ mask_sh 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ mask_sh 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ mask_sh 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \ mask_sh 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ mask_sh 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \ mask_sh 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ mask_sh 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \ mask_sh 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ mask_sh 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ mask_sh 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ mask_sh 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ mask_sh 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ mask_sh 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ mask_sh 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ mask_sh 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ mask_sh 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \ mask_sh 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ mask_sh 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \ mask_sh 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ mask_sh 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ mask_sh 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ mask_sh 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ mask_sh 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ mask_sh 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ mask_sh 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \ mask_sh 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ mask_sh 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ mask_sh 328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \ mask_sh 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \ mask_sh 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ mask_sh 331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh) mask_sh 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\ mask_sh 334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_REG_LIST_SH_MASK_DCN(mask_sh),\ mask_sh 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\ mask_sh 336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\ mask_sh 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\ mask_sh 338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\ mask_sh 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\ mask_sh 340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\ mask_sh 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\ mask_sh 342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\ mask_sh 343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\ mask_sh 344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\ mask_sh 345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\ mask_sh 346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\ mask_sh 347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\ mask_sh 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \ mask_sh 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \ mask_sh 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ mask_sh 351 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ mask_sh 352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ mask_sh 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ mask_sh 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ mask_sh 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ mask_sh 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \ mask_sh 357 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \ mask_sh 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \ mask_sh 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ mask_sh 360 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ mask_sh 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ mask_sh 363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ mask_sh 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ mask_sh 365 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ mask_sh 367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ mask_sh 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ mask_sh 371 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ mask_sh 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ mask_sh 373 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ mask_sh 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ mask_sh 375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ mask_sh 377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ mask_sh 378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ mask_sh 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ mask_sh 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ mask_sh 387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ mask_sh 388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ mask_sh 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ mask_sh 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ mask_sh 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ mask_sh 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ mask_sh 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ mask_sh 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ mask_sh 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ mask_sh 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ mask_sh 400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ mask_sh 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ mask_sh 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ mask_sh 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ mask_sh 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ mask_sh 407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ mask_sh 413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ mask_sh 414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ mask_sh 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ mask_sh 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ mask_sh 417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ mask_sh 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ mask_sh 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ mask_sh 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ mask_sh 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \ mask_sh 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ mask_sh 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ mask_sh 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ mask_sh 425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ mask_sh 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ mask_sh 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \ mask_sh 429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ mask_sh 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \ mask_sh 431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \ mask_sh 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 435 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 436 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh) mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h #define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\ mask_sh 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ mask_sh 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ mask_sh 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ mask_sh 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ mask_sh 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ mask_sh 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ mask_sh 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ mask_sh 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ mask_sh 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ mask_sh 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ mask_sh 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ mask_sh 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ mask_sh 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\ mask_sh 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ mask_sh 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ mask_sh 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ mask_sh 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ mask_sh 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ mask_sh 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ mask_sh 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ mask_sh 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ mask_sh 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ mask_sh 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ mask_sh 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ mask_sh 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ mask_sh 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ mask_sh 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ mask_sh 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ mask_sh 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ mask_sh 129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh) mask_sh 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h #define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ mask_sh 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ mask_sh 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ mask_sh 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ mask_sh 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ mask_sh 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ mask_sh 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ mask_sh 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ mask_sh 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ mask_sh 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ mask_sh 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ mask_sh 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ mask_sh 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ mask_sh 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ mask_sh 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ mask_sh 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ mask_sh 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ mask_sh 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh) mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h #define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ mask_sh 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh) mask_sh 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h #define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh) mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ mask_sh 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ mask_sh 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ mask_sh 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ mask_sh 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ mask_sh 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ mask_sh 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ mask_sh 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ mask_sh 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ mask_sh 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ mask_sh 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ mask_sh 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ mask_sh 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ mask_sh 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ mask_sh 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ mask_sh 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ mask_sh 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ mask_sh 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ mask_sh 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ mask_sh 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ mask_sh 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ mask_sh 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ mask_sh 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ mask_sh 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ mask_sh 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ mask_sh 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ mask_sh 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ mask_sh 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ mask_sh 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ mask_sh 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ mask_sh 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ mask_sh 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ mask_sh 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ mask_sh 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ mask_sh 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ mask_sh 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ mask_sh 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ mask_sh 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ mask_sh 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ mask_sh 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ mask_sh 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ mask_sh 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ mask_sh 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ mask_sh 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ mask_sh 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ mask_sh 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ mask_sh 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ mask_sh 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ mask_sh 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ mask_sh 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ mask_sh 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ mask_sh 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ mask_sh 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ mask_sh 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ mask_sh 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ mask_sh 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ mask_sh 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ mask_sh 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ mask_sh 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ mask_sh 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ mask_sh 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ mask_sh 328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ mask_sh 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ mask_sh 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ mask_sh 331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ mask_sh 332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ mask_sh 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ mask_sh 334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ mask_sh 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ mask_sh 336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ mask_sh 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ mask_sh 338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ mask_sh 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ mask_sh 340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ mask_sh 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ mask_sh 342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ mask_sh 343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ mask_sh 344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ mask_sh 345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ mask_sh 346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ mask_sh 347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ mask_sh 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ mask_sh 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ mask_sh 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ mask_sh 351 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ mask_sh 352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ mask_sh 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ mask_sh 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ mask_sh 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ mask_sh 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ mask_sh 357 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ mask_sh 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ mask_sh 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ mask_sh 360 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ mask_sh 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ mask_sh 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ mask_sh 363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ mask_sh 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) mask_sh 366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ mask_sh 367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ mask_sh 368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ mask_sh 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ mask_sh 370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) mask_sh 373 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define HUBP_MASK_SH_LIST_DCN(mask_sh)\ mask_sh 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) mask_sh 377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ mask_sh 378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ mask_sh 379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ mask_sh 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ mask_sh 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ mask_sh 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ mask_sh 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ mask_sh 384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ mask_sh 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ mask_sh 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ mask_sh 387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) mask_sh 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ mask_sh 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_MASK_SH_LIST_DCN(mask_sh),\ mask_sh 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ mask_sh 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ mask_sh 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ mask_sh 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ mask_sh 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ mask_sh 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ mask_sh 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ mask_sh 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ mask_sh 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ mask_sh 400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ mask_sh 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ mask_sh 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ mask_sh 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ mask_sh 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ mask_sh 405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ mask_sh 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ mask_sh 407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ mask_sh 408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ mask_sh 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ mask_sh 410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ mask_sh 411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ mask_sh 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ mask_sh 413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ mask_sh 414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ mask_sh 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h #define IPP_MASK_SH_LIST_DCN(mask_sh) \ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh) mask_sh 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h #define IPP_MASK_SH_LIST_DCN10(mask_sh) \ mask_sh 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_MASK_SH_LIST_DCN(mask_sh),\ mask_sh 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ mask_sh 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ mask_sh 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh) mask_sh 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h #define IPP_MASK_SH_LIST_DCN20(mask_sh) \ mask_sh 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_MASK_SH_LIST_DCN(mask_sh), \ mask_sh 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ mask_sh 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ mask_sh 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) mask_sh 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ mask_sh 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ mask_sh 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ mask_sh 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ mask_sh 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ mask_sh 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ mask_sh 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh) mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h #define OPP_MASK_SH_LIST_DCN(mask_sh) \ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ mask_sh 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ mask_sh 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ mask_sh 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ mask_sh 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\ mask_sh 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh), \ mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_MASK_SH_LIST_DCN(mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh) mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ mask_sh 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ mask_sh 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ mask_sh 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ mask_sh 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ mask_sh 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ mask_sh 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ mask_sh 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ mask_sh 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ mask_sh 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ mask_sh 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ mask_sh 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ mask_sh 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ mask_sh 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ mask_sh 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ mask_sh 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ mask_sh 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ mask_sh 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ mask_sh 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ mask_sh 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ mask_sh 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ mask_sh 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ mask_sh 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ mask_sh 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ mask_sh 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ mask_sh 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ mask_sh 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ mask_sh 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ mask_sh 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ mask_sh 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ mask_sh 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ mask_sh 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ mask_sh 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ mask_sh 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ mask_sh 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ mask_sh 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ mask_sh 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ mask_sh 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ mask_sh 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ mask_sh 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) mask_sh 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ mask_sh 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ mask_sh 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ mask_sh 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ mask_sh 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ mask_sh 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ mask_sh 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ mask_sh 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ mask_sh 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ mask_sh 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ mask_sh 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ mask_sh 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ mask_sh 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ mask_sh 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ mask_sh 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ mask_sh 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ mask_sh 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ mask_sh 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ mask_sh 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ mask_sh 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ mask_sh 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ mask_sh 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ mask_sh 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\ mask_sh 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\ mask_sh 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\ mask_sh 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\ mask_sh 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ mask_sh 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ mask_sh 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ mask_sh 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\ mask_sh 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ mask_sh 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ mask_sh 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ mask_sh 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ mask_sh 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ mask_sh 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ mask_sh 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ mask_sh 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\ mask_sh 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ mask_sh 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ mask_sh 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ mask_sh 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ mask_sh 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ mask_sh 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ mask_sh 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ mask_sh 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ mask_sh 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ mask_sh 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ mask_sh 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ mask_sh 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ mask_sh 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ mask_sh 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ mask_sh 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ mask_sh 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ mask_sh 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ mask_sh 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) mask_sh 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ mask_sh 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) mask_sh 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ mask_sh 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ mask_sh 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ mask_sh 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ mask_sh 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ mask_sh 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ mask_sh 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ mask_sh 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh) mask_sh 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ mask_sh 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ mask_sh 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ mask_sh 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ mask_sh 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh) mask_sh 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_REG_LIST_SH_MASK_DCN(mask_sh), \ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \ mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ mask_sh 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ mask_sh 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ mask_sh 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ mask_sh 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ mask_sh 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ mask_sh 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ mask_sh 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ mask_sh 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ mask_sh 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ mask_sh 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ mask_sh 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ mask_sh 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ mask_sh 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ mask_sh 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ mask_sh 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ mask_sh 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ mask_sh 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_B, mask_sh), \ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_G, mask_sh), \ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \ mask_sh 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ mask_sh 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \ mask_sh 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ mask_sh 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \ mask_sh 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ mask_sh 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ mask_sh 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ mask_sh 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ mask_sh 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ mask_sh 284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ mask_sh 285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ mask_sh 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ mask_sh 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ mask_sh 288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ mask_sh 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ mask_sh 290 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ mask_sh 291 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ mask_sh 292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ mask_sh 293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ mask_sh 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ mask_sh 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ mask_sh 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ mask_sh 297 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ mask_sh 298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ mask_sh 299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ mask_sh 300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ mask_sh 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ mask_sh 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ mask_sh 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ mask_sh 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ mask_sh 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ mask_sh 306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ mask_sh 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ mask_sh 308 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ mask_sh 309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ mask_sh 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ mask_sh 311 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ mask_sh 312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ mask_sh 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ mask_sh 314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ mask_sh 315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ mask_sh 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ mask_sh 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ mask_sh 318 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ mask_sh 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ mask_sh 320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ mask_sh 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ mask_sh 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ mask_sh 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ mask_sh 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ mask_sh 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ mask_sh 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ mask_sh 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ mask_sh 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ mask_sh 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ mask_sh 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ mask_sh 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ mask_sh 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ mask_sh 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ mask_sh 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ mask_sh 335 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ mask_sh 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ mask_sh 337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ mask_sh 338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ mask_sh 339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ mask_sh 340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ mask_sh 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ mask_sh 342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ mask_sh 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ mask_sh 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \ mask_sh 346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \ mask_sh 347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \ mask_sh 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \ mask_sh 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \ mask_sh 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ mask_sh 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \ mask_sh 352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_INDEX, CM_3DLUT_INDEX, mask_sh), \ mask_sh 353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \ mask_sh 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA1, mask_sh), \ mask_sh 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_DATA_30BIT, CM_3DLUT_DATA_30BIT, mask_sh), \ mask_sh 356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \ mask_sh 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \ mask_sh 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \ mask_sh 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \ mask_sh 360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \ mask_sh 361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \ mask_sh 362 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \ mask_sh 363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh), \ mask_sh 365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 366 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh), \ mask_sh 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh), \ mask_sh 369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh), \ mask_sh 371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh), \ mask_sh 373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 377 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ mask_sh 379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ mask_sh 380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ mask_sh 381 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ mask_sh 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ mask_sh 383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ mask_sh 384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ mask_sh 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ mask_sh 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ mask_sh 387 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ mask_sh 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ mask_sh 389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ mask_sh 390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ mask_sh 391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ mask_sh 392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ mask_sh 393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ mask_sh 394 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ mask_sh 395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ mask_sh 396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ mask_sh 397 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ mask_sh 398 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ mask_sh 399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ mask_sh 400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ mask_sh 401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ mask_sh 402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ mask_sh 403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ mask_sh 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ mask_sh 405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ mask_sh 406 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ mask_sh 407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ mask_sh 408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ mask_sh 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ mask_sh 410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ mask_sh 411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ mask_sh 412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ mask_sh 413 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ mask_sh 414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ mask_sh 415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ mask_sh 416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ mask_sh 417 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ mask_sh 418 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ mask_sh 419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ mask_sh 420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ mask_sh 421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ mask_sh 422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ mask_sh 423 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ mask_sh 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ mask_sh 425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ mask_sh 426 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ mask_sh 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ mask_sh 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ mask_sh 429 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ mask_sh 430 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ mask_sh 431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ mask_sh 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ mask_sh 433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ mask_sh 434 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ mask_sh 435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ mask_sh 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ mask_sh 437 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ mask_sh 438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ mask_sh 439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ mask_sh 440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ mask_sh 441 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ mask_sh 442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh), \ mask_sh 443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ mask_sh 444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh), \ mask_sh 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ mask_sh 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh), \ mask_sh 447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ mask_sh 448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh), \ mask_sh 449 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ mask_sh 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh), \ mask_sh 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ mask_sh 452 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh), \ mask_sh 453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ mask_sh 454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ mask_sh 455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ mask_sh 456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ mask_sh 457 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ mask_sh 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ mask_sh 459 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ mask_sh 460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ mask_sh 461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ mask_sh 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ mask_sh 463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ mask_sh 464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ mask_sh 465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ mask_sh 466 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ mask_sh 467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ mask_sh 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ mask_sh 469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ mask_sh 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ mask_sh 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ mask_sh 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ mask_sh 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ mask_sh 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ mask_sh 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ mask_sh 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ mask_sh 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ mask_sh 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ mask_sh 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ mask_sh 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ mask_sh 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ mask_sh 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ mask_sh 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ mask_sh 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ mask_sh 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ mask_sh 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ mask_sh 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ mask_sh 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ mask_sh 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ mask_sh 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ mask_sh 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ mask_sh 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ mask_sh 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ mask_sh 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ mask_sh 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ mask_sh 496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ mask_sh 497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ mask_sh 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ mask_sh 499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ mask_sh 500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ mask_sh 501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ mask_sh 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ mask_sh 503 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ mask_sh 504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ mask_sh 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ mask_sh 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ mask_sh 507 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ mask_sh 508 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ mask_sh 509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ mask_sh 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ mask_sh 511 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ mask_sh 512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ mask_sh 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ mask_sh 514 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ mask_sh 515 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ mask_sh 516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ mask_sh 517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ mask_sh 518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ mask_sh 519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ mask_sh 520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ mask_sh 521 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ mask_sh 522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \ mask_sh 523 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \ mask_sh 524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, mask_sh), \ mask_sh 525 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \ mask_sh 526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh), \ mask_sh 527 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \ mask_sh 528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ mask_sh 529 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 531 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ mask_sh 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ mask_sh 535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ mask_sh 536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ mask_sh 537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \ mask_sh 538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \ mask_sh 539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \ mask_sh 540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \ mask_sh 541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ mask_sh 542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ mask_sh 543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ mask_sh 544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ mask_sh 545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ mask_sh 546 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ mask_sh 547 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ mask_sh 548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ mask_sh 549 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ mask_sh 550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ mask_sh 551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ mask_sh 552 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ mask_sh 553 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ mask_sh 554 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ mask_sh 555 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ mask_sh 556 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ mask_sh 557 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ mask_sh 558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ mask_sh 559 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ mask_sh 560 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ mask_sh 561 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh) mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h #define DSC_REG_LIST_SH_MASK_DCN20(mask_sh)\ mask_sh 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \ mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \ mask_sh 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ mask_sh 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ mask_sh 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \ mask_sh 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \ mask_sh 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ mask_sh 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \ mask_sh 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \ mask_sh 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \ mask_sh 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \ mask_sh 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \ mask_sh 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \ mask_sh 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \ mask_sh 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \ mask_sh 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \ mask_sh 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ mask_sh 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \ mask_sh 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \ mask_sh 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \ mask_sh 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \ mask_sh 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \ mask_sh 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \ mask_sh 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \ mask_sh 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \ mask_sh 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \ mask_sh 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \ mask_sh 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \ mask_sh 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \ mask_sh 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \ mask_sh 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \ mask_sh 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \ mask_sh 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \ mask_sh 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \ mask_sh 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \ mask_sh 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \ mask_sh 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \ mask_sh 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \ mask_sh 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \ mask_sh 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \ mask_sh 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \ mask_sh 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \ mask_sh 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \ mask_sh 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \ mask_sh 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \ mask_sh 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \ mask_sh 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \ mask_sh 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \ mask_sh 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \ mask_sh 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \ mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \ mask_sh 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \ mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \ mask_sh 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \ mask_sh 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \ mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \ mask_sh 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \ mask_sh 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \ mask_sh 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \ mask_sh 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \ mask_sh 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \ mask_sh 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \ mask_sh 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \ mask_sh 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \ mask_sh 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \ mask_sh 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \ mask_sh 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \ mask_sh 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \ mask_sh 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \ mask_sh 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \ mask_sh 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \ mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) mask_sh 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h #define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ mask_sh 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_ENABLE, WB_ENABLE, mask_sh),\ mask_sh 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ mask_sh 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ mask_sh 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ mask_sh 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\ mask_sh 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ mask_sh 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\ mask_sh 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ mask_sh 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\ mask_sh 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\ mask_sh 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\ mask_sh 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\ mask_sh 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ mask_sh 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ mask_sh 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ mask_sh 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\ mask_sh 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\ mask_sh 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ mask_sh 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ mask_sh 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\ mask_sh 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\ mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\ mask_sh 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh) mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh) mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h #define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ mask_sh 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ mask_sh 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ mask_sh 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ mask_sh 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ mask_sh 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ mask_sh 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ mask_sh 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ mask_sh 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ mask_sh 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ mask_sh 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ mask_sh 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ mask_sh 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ mask_sh 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ mask_sh 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ mask_sh 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ mask_sh 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) mask_sh 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ mask_sh 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) mask_sh 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ mask_sh 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) mask_sh 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h #define UNIPHY_MASK_SH_LIST(mask_sh)\ mask_sh 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh) mask_sh 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\ mask_sh 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\ mask_sh 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ mask_sh 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ mask_sh 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ mask_sh 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\ mask_sh 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\ mask_sh 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\ mask_sh 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\ mask_sh 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\ mask_sh 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ mask_sh 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h UNIPHY_MASK_SH_LIST(mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ mask_sh 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ mask_sh 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ mask_sh 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ mask_sh 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh) mask_sh 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h #define MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ mask_sh 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ mask_sh 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ mask_sh 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ mask_sh 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ mask_sh 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\ mask_sh 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\ mask_sh 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\ mask_sh 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\ mask_sh 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\ mask_sh 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\ mask_sh 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\ mask_sh 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\ mask_sh 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\ mask_sh 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\ mask_sh 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\ mask_sh 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\ mask_sh 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\ mask_sh 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\ mask_sh 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\ mask_sh 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\ mask_sh 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\ mask_sh 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\ mask_sh 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\ mask_sh 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\ mask_sh 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\ mask_sh 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\ mask_sh 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\ mask_sh 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\ mask_sh 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\ mask_sh 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\ mask_sh 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\ mask_sh 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\ mask_sh 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\ mask_sh 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\ mask_sh 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\ mask_sh 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\ mask_sh 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\ mask_sh 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\ mask_sh 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\ mask_sh 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\ mask_sh 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\ mask_sh 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\ mask_sh 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\ mask_sh 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\ mask_sh 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\ mask_sh 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\ mask_sh 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\ mask_sh 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\ mask_sh 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\ mask_sh 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\ mask_sh 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\ mask_sh 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\ mask_sh 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ mask_sh 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ mask_sh 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ mask_sh 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ mask_sh 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\ mask_sh 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\ mask_sh 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ mask_sh 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ mask_sh 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ mask_sh 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ mask_sh 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ mask_sh 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ mask_sh 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ mask_sh 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ mask_sh 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ mask_sh 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ mask_sh 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ mask_sh 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ mask_sh 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ mask_sh 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ mask_sh 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ mask_sh 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ mask_sh 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ mask_sh 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ mask_sh 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ mask_sh 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ mask_sh 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ mask_sh 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ mask_sh 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ mask_sh 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ mask_sh 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ mask_sh 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ mask_sh 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ mask_sh 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ mask_sh 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\ mask_sh 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ mask_sh 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\ mask_sh 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\ mask_sh 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\ mask_sh 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\ mask_sh 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ mask_sh 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\ mask_sh 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\ mask_sh 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\ mask_sh 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\ mask_sh 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\ mask_sh 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\ mask_sh 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\ mask_sh 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\ mask_sh 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\ mask_sh 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\ mask_sh 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\ mask_sh 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\ mask_sh 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\ mask_sh 270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\ mask_sh 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\ mask_sh 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\ mask_sh 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\ mask_sh 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\ mask_sh 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\ mask_sh 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\ mask_sh 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh) mask_sh 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h #define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ mask_sh 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ mask_sh 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ mask_sh 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ mask_sh 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ mask_sh 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ mask_sh 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ mask_sh 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ mask_sh 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ mask_sh 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ mask_sh 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ mask_sh 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ mask_sh 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ mask_sh 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ mask_sh 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ mask_sh 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ mask_sh 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ mask_sh 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\ mask_sh 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ mask_sh 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ mask_sh 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\ mask_sh 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ mask_sh 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\ mask_sh 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ mask_sh 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\ mask_sh 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\ mask_sh 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\ mask_sh 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\ mask_sh 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\ mask_sh 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ mask_sh 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ mask_sh 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ mask_sh 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ mask_sh 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\ mask_sh 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\ mask_sh 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\ mask_sh 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ mask_sh 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\ mask_sh 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ mask_sh 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ mask_sh 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ mask_sh 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ mask_sh 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ mask_sh 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ mask_sh 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh) mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h #define OPP_DPG_MASK_SH_LIST(mask_sh) \ mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR1_B_CB, mask_sh), \ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_RAMP0_OFFSET, mask_sh), \ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC1, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, mask_sh) mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h #define OPP_MASK_SH_LIST_DCN20(mask_sh) \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_MASK_SH_LIST_DCN(mask_sh), \ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_DPG_MASK_SH_LIST(mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh), \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(FMT0_FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, mask_sh) mask_sh 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ mask_sh 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ mask_sh 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\ mask_sh 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ mask_sh 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\ mask_sh 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ mask_sh 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ mask_sh 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh) mask_sh 531 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ mask_sh 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ mask_sh 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ mask_sh 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) mask_sh 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h #define SE_COMMON_MASK_SH_LIST_DCN20(mask_sh)\ mask_sh 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ mask_sh 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ mask_sh 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ mask_sh 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ mask_sh 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\ mask_sh 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\ mask_sh 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\ mask_sh 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\ mask_sh 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\ mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\ mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\ mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, mask_sh),\ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_DSC_BYTES_PER_PIXEL, DP_DSC_BYTES_PER_PIXEL, mask_sh),\ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\ mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh) mask_sh 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h #define DCN20_VMID_MASK_SH_LIST(mask_sh)\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\ mask_sh 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\ mask_sh 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ mask_sh 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh) mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \ mask_sh 87 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \ mask_sh 88 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \ mask_sh 89 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \ mask_sh 90 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \ mask_sh 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \ mask_sh 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \ mask_sh 93 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \ mask_sh 94 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \ mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \ mask_sh 96 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \ mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \ mask_sh 99 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ mask_sh 101 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ mask_sh 102 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh) mask_sh 104 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ mask_sh 105 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_MASK_SH_LIST_HVM(mask_sh),\ mask_sh 106 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ mask_sh 107 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ mask_sh 108 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ mask_sh 109 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ mask_sh 110 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ mask_sh 111 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ mask_sh 112 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ mask_sh 113 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ mask_sh 114 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh) mask_sh 44 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h #define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\ mask_sh 45 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ mask_sh 46 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ mask_sh 47 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ mask_sh 48 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ mask_sh 49 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ mask_sh 51 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ mask_sh 52 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ mask_sh 53 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ mask_sh 54 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ mask_sh 55 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ mask_sh 56 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ mask_sh 57 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ mask_sh 58 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ mask_sh 59 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ mask_sh 60 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ mask_sh 61 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ mask_sh 62 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ mask_sh 63 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ mask_sh 64 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ mask_sh 65 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ mask_sh 66 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ mask_sh 67 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ mask_sh 68 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ mask_sh 69 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ mask_sh 70 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ mask_sh 71 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ mask_sh 72 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ mask_sh 73 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ mask_sh 74 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ mask_sh 75 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ mask_sh 76 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ mask_sh 77 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ mask_sh 78 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ mask_sh 79 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ mask_sh 80 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ mask_sh 81 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ mask_sh 82 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ mask_sh 83 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ mask_sh 84 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ mask_sh 85 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ mask_sh 86 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ mask_sh 87 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ mask_sh 88 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ mask_sh 89 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ mask_sh 90 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ mask_sh 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\ mask_sh 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\ mask_sh 93 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\ mask_sh 94 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\ mask_sh 95 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ mask_sh 96 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ mask_sh 97 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ mask_sh 98 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) mask_sh 100 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h #define HUBP_MASK_SH_LIST_DCN21(mask_sh)\ mask_sh 101 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\ mask_sh 102 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh) mask_sh 382 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ mask_sh 383 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ mask_sh 384 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ mask_sh 385 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) mask_sh 52 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c #define HPD_MASK_SH_LIST_DCE8(mask_sh) \ mask_sh 53 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c .DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\ mask_sh 54 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\ mask_sh 55 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c .DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\ mask_sh 56 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c .DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh mask_sh 100 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ mask_sh 101 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ mask_sh 102 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ mask_sh 103 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\ mask_sh 104 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\ mask_sh 105 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\ mask_sh 106 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh) mask_sh 108 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h #define DDC_MASK_SH_LIST(mask_sh) \ mask_sh 109 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h DDC_MASK_SH_LIST_COMMON(mask_sh),\ mask_sh 110 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ mask_sh 111 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) mask_sh 114 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ mask_sh 115 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h {DDC_MASK_SH_LIST_COMMON(mask_sh),\ mask_sh 118 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} mask_sh 48 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h #define GENERIC_MASK_SH_LIST(mask_sh, cd) \ mask_sh 49 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h {(DC_GENERIC ## cd ##__GENERIC ## cd ##_EN## mask_sh),\ mask_sh 50 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h (DC_GENERIC ## cd ##__GENERIC ## cd ##_SEL## mask_sh)} mask_sh 57 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h #define HPD_MASK_SH_LIST(mask_sh) \ mask_sh 58 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED, mask_sh),\ mask_sh 59 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\ mask_sh 60 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\ mask_sh 61 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh) mask_sh 109 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ mask_sh 110 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ mask_sh 111 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) mask_sh 113 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ mask_sh 114 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ mask_sh 115 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) mask_sh 117 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_MASK_SH_LIST_RV1(mask_sh) \ mask_sh 118 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ mask_sh 119 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\ mask_sh 120 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ mask_sh 121 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh), mask_sh 124 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \ mask_sh 125 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ mask_sh 126 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ mask_sh 127 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh) mask_sh 129 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_MASK_SH_LIST_NV10(mask_sh) \ mask_sh 130 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ mask_sh 131 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\ mask_sh 132 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)