mask_reg 682 drivers/atm/iphase.h ffreg_t mask_reg; /* Mask Register */ mask_reg 720 drivers/atm/iphase.h rreg_t mask_reg; /* Mask Register */ mask_reg 173 drivers/bus/omap_l3_noc.c void __iomem *base, *mask_reg; mask_reg 211 drivers/bus/omap_l3_noc.c mask_reg = base + flag_mux->offset + mask_reg 213 drivers/bus/omap_l3_noc.c mask_val = readl_relaxed(mask_reg); mask_reg 215 drivers/bus/omap_l3_noc.c writel_relaxed(mask_val, mask_reg); mask_reg 958 drivers/edac/amd64_edac.c u32 mask_reg, mask_reg_sec; mask_reg 990 drivers/edac/amd64_edac.c mask_reg = umc_mask_reg + (cs * 4); mask_reg 993 drivers/edac/amd64_edac.c if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) mask_reg 995 drivers/edac/amd64_edac.c umc, cs, *mask, mask_reg); mask_reg 715 drivers/gpio/gpio-omap.c void __iomem *mask_reg = bank->base + mask_reg 720 drivers/gpio/gpio-omap.c writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); mask_reg 729 drivers/gpio/gpio-omap.c void __iomem *mask_reg = bank->base + mask_reg 734 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.wake_en, mask_reg); mask_reg 61 drivers/irqchip/irq-csky-apb-intc.c u32 mask_reg, u32 irq_base) mask_reg 67 drivers/irqchip/irq-csky-apb-intc.c gc->chip_types[0].regs.mask = mask_reg; mask_reg 44 drivers/irqchip/spear-shirq.c u32 mask_reg; mask_reg 62 drivers/irqchip/spear-shirq.c u32 __iomem *reg = shirq->base + shirq->mask_reg; mask_reg 74 drivers/irqchip/spear-shirq.c u32 __iomem *reg = shirq->base + shirq->mask_reg; mask_reg 94 drivers/irqchip/spear-shirq.c .mask_reg = SPEAR300_INT_ENB_MASK_REG, mask_reg 344 drivers/mfd/88pm860x-core.c int mask_reg; mask_reg 352 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_1, mask_reg 357 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_1, mask_reg 362 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_1, mask_reg 367 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_1, mask_reg 372 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_1, mask_reg 377 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_1, mask_reg 382 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 387 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 392 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 397 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 402 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 407 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 412 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 417 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_2, mask_reg 422 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 427 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 432 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 437 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 442 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 447 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 452 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 457 drivers/mfd/88pm860x-core.c .mask_reg = PM8607_INT_MASK_3, mask_reg 505 drivers/mfd/88pm860x-core.c switch (irq_data->mask_reg) { mask_reg 331 drivers/mfd/max8925-core.c int mask_reg; mask_reg 341 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ1_MASK, mask_reg 346 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ1_MASK, mask_reg 351 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ1_MASK, mask_reg 356 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 361 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 366 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 371 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 376 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 381 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 386 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 391 drivers/mfd/max8925-core.c .mask_reg = MAX8925_CHG_IRQ2_MASK, mask_reg 396 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 401 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 406 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 411 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 416 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 421 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 426 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 431 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, mask_reg 436 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ2_MASK, mask_reg 441 drivers/mfd/max8925-core.c .mask_reg = MAX8925_ON_OFF_IRQ2_MASK, mask_reg 446 drivers/mfd/max8925-core.c .mask_reg = MAX8925_RTC_IRQ_MASK, mask_reg 452 drivers/mfd/max8925-core.c .mask_reg = MAX8925_RTC_IRQ_MASK, mask_reg 458 drivers/mfd/max8925-core.c .mask_reg = MAX8925_TSC_IRQ_MASK, mask_reg 465 drivers/mfd/max8925-core.c .mask_reg = MAX8925_TSC_IRQ_MASK, mask_reg 564 drivers/mfd/max8925-core.c switch (irq_data->mask_reg) { mask_reg 113 drivers/mfd/max8997-irq.c u8 mask_reg = max8997_mask_reg[i]; mask_reg 116 drivers/mfd/max8997-irq.c if (mask_reg == MAX8997_REG_INVALID || mask_reg 55 drivers/mfd/tps6586x.c u8 mask_reg; mask_reg 61 drivers/mfd/tps6586x.c .mask_reg = (_reg) - TPS6586X_INT_MASK1, \ mask_reg 131 drivers/mfd/tps6586x.c u8 mask_reg[5]; mask_reg 241 drivers/mfd/tps6586x.c tps6586x->mask_reg[data->mask_reg] &= ~data->mask_mask; mask_reg 252 drivers/mfd/tps6586x.c tps6586x->mask_reg[data->mask_reg] |= data->mask_mask; mask_reg 261 drivers/mfd/tps6586x.c for (i = 0; i < ARRAY_SIZE(tps6586x->mask_reg); i++) { mask_reg 265 drivers/mfd/tps6586x.c tps6586x->mask_reg[i]); mask_reg 350 drivers/mfd/tps6586x.c tps6586x->mask_reg[i] = 0xff; mask_reg 5956 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 data_reg, mask_reg, cfg; mask_reg 5990 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx; mask_reg 5992 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { mask_reg 5994 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adap, mask_reg, ~tp->mask[i]); mask_reg 6023 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 data_reg, mask_reg; mask_reg 6044 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst; mask_reg 6046 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { mask_reg 6047 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c tp->mask[i] = ~t4_read_reg(adap, mask_reg); mask_reg 846 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c u32 offset, mask_reg; mask_reg 868 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c mask_reg = legacy_intrp->tgt_mask_reg; mask_reg 869 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c adapter->tgt_mask_reg = qlcnic_get_ioaddr(ahw, mask_reg); mask_reg 227 drivers/net/ethernet/sun/niu.c unsigned long mask_reg, bits; mask_reg 234 drivers/net/ethernet/sun/niu.c mask_reg = LD_IM0(ldn); mask_reg 237 drivers/net/ethernet/sun/niu.c mask_reg = LD_IM1(ldn - 64); mask_reg 241 drivers/net/ethernet/sun/niu.c val = nr64(mask_reg); mask_reg 246 drivers/net/ethernet/sun/niu.c nw64(mask_reg, val); mask_reg 1094 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 mask_reg; mask_reg 1153 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_clear_bit(trans, causes[i].mask_reg, mask_reg 36 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 42 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 48 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 54 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 60 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 66 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 72 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 78 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 84 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 90 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CRIMR, mask_reg 96 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CRIMR, mask_reg 102 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CRIMR, mask_reg 108 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CRIMR, mask_reg 114 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CRIMR, mask_reg 120 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 126 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 132 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 138 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 144 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 150 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 156 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 162 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 168 drivers/soc/fsl/qe/qe_ic.c .mask_reg = QEIC_CIMR, mask_reg 204 drivers/soc/fsl/qe/qe_ic.c temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); mask_reg 205 drivers/soc/fsl/qe/qe_ic.c qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, mask_reg 220 drivers/soc/fsl/qe/qe_ic.c temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); mask_reg 221 drivers/soc/fsl/qe/qe_ic.c qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, mask_reg 93 drivers/soc/fsl/qe/qe_ic.h u32 mask_reg; /* Mask register offset */