mask_offset        26 arch/arm/mach-davinci/include/mach/mux.h 	const unsigned char mask_offset;
mask_offset        72 arch/arm/mach-davinci/mux.c 		mask = (cfg->mask << cfg->mask_offset);
mask_offset        76 arch/arm/mach-davinci/mux.c 		tmp2 = (cfg->mode << cfg->mask_offset);
mask_offset        24 arch/arm/mach-davinci/mux.h 			.mask_offset = mode_offset,			\
mask_offset        35 arch/arm/mach-davinci/mux.h 			.mask_offset = mode_offset,			\
mask_offset        46 arch/arm/mach-davinci/mux.h 			.mask_offset = mode_offset,			\
mask_offset        29 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mask_offset        43 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mask_offset        54 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mask_offset        66 arch/arm/mach-omap1/include/mach/mux.h 					.mask_offset = mode_offset, \
mask_offset       109 arch/arm/mach-omap1/include/mach/mux.h 	const unsigned char mask_offset;
mask_offset       348 arch/arm/mach-omap1/mux.c 		mask = (0x7 << cfg->mask_offset);
mask_offset       352 arch/arm/mach-omap1/mux.c 		tmp2 = (cfg->mask << cfg->mask_offset);
mask_offset        46 arch/arm/plat-orion/gpio.c 	int			mask_offset;
mask_offset        83 arch/arm/plat-orion/gpio.c 	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
mask_offset        88 arch/arm/plat-orion/gpio.c 	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
mask_offset       525 arch/arm/plat-orion/gpio.c 			    void __iomem *base, int mask_offset,
mask_offset       561 arch/arm/plat-orion/gpio.c 	ochip->mask_offset = mask_offset;
mask_offset       590 arch/arm/plat-orion/gpio.c 	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
mask_offset       598 arch/arm/plat-orion/gpio.c 	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
mask_offset        35 arch/arm/plat-orion/include/plat/orion-gpio.h 			    void __iomem *base, int mask_offset,
mask_offset        60 drivers/irqchip/irq-brcmstb-l2.c 	int mask_offset;
mask_offset       101 drivers/irqchip/irq-brcmstb-l2.c 		~(irq_reg_readl(b->gc, b->mask_offset));
mask_offset       227 drivers/irqchip/irq-brcmstb-l2.c 	data->mask_offset = init_params->cpu_mask_status;
mask_offset       127 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h 					u32 mask_offset;
mask_offset       312 drivers/pinctrl/mediatek/mtk-eint.c 	int offset, mask_offset, index, virq;
mask_offset       322 drivers/pinctrl/mediatek/mtk-eint.c 			mask_offset = eint_num >> 5;
mask_offset       333 drivers/pinctrl/mediatek/mtk-eint.c 			if (eint->wake_mask[mask_offset] & BIT(offset) &&
mask_offset       334 drivers/pinctrl/mediatek/mtk-eint.c 			    !(eint->cur_mask[mask_offset] & BIT(offset))) {