mask_clk_reg 52 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); mask_clk_reg 81 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (i2c.mask_clk_reg) mask_clk_reg 385 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c amdgpu_connector->ddc_bus->rec.mask_clk_reg, mask_clk_reg 51 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg); mask_clk_reg 53 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_clk_reg, temp); mask_clk_reg 71 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; mask_clk_reg 72 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_clk_reg, temp); mask_clk_reg 73 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg); mask_clk_reg 90 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; mask_clk_reg 91 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_clk_reg, temp); mask_clk_reg 92 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c temp = RREG32(rec->mask_clk_reg); mask_clk_reg 153 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t mask_clk_reg; mask_clk_reg 96 drivers/gpu/drm/radeon/radeon_atombios.c i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; mask_clk_reg 125 drivers/gpu/drm/radeon/radeon_atombios.c if (i2c.mask_clk_reg) mask_clk_reg 495 drivers/gpu/drm/radeon/radeon_combios.c i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; mask_clk_reg 504 drivers/gpu/drm/radeon/radeon_combios.c i2c.mask_clk_reg = RADEON_MDGPIO_MASK; mask_clk_reg 513 drivers/gpu/drm/radeon/radeon_combios.c i2c.mask_clk_reg = ddc_line; mask_clk_reg 2233 drivers/gpu/drm/radeon/radeon_combios.c ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) mask_clk_reg 786 drivers/gpu/drm/radeon/radeon_display.c radeon_connector->ddc_bus->rec.mask_clk_reg, mask_clk_reg 99 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(chan->rec.mask_clk_reg); mask_clk_reg 101 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(chan->rec.mask_clk_reg, tmp); mask_clk_reg 132 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg); mask_clk_reg 134 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, temp); mask_clk_reg 152 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; mask_clk_reg 153 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, temp); mask_clk_reg 154 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg); mask_clk_reg 171 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; mask_clk_reg 172 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, temp); mask_clk_reg 173 drivers/gpu/drm/radeon/radeon_i2c.c temp = RREG32(rec->mask_clk_reg); mask_clk_reg 374 drivers/gpu/drm/radeon/radeon_i2c.c switch (rec->mask_clk_reg) { mask_clk_reg 386 drivers/gpu/drm/radeon/radeon_i2c.c switch (rec->mask_clk_reg) { mask_clk_reg 402 drivers/gpu/drm/radeon/radeon_i2c.c switch (rec->mask_clk_reg) { mask_clk_reg 421 drivers/gpu/drm/radeon/radeon_i2c.c switch (rec->mask_clk_reg) { mask_clk_reg 442 drivers/gpu/drm/radeon/radeon_i2c.c switch (rec->mask_clk_reg) { mask_clk_reg 601 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->mask_clk_reg); mask_clk_reg 603 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, tmp); mask_clk_reg 604 drivers/gpu/drm/radeon/radeon_i2c.c tmp = RREG32(rec->mask_clk_reg); mask_clk_reg 653 drivers/gpu/drm/radeon/radeon_i2c.c switch (rec->mask_clk_reg) { mask_clk_reg 123 drivers/gpu/drm/radeon/radeon_mode.h uint32_t mask_clk_reg;