mask5 192 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5) mask5 199 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); mask5 208 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5, mask5 216 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); mask5 226 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5, mask5 235 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); mask5 246 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift5, uint32_t mask5, uint32_t *field_value5, mask5 256 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); mask5 414 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5); mask5 421 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5, mask5 429 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5, mask5 438 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift5, uint32_t mask5, uint32_t *field_value5, mask5 158 drivers/net/hamradio/hdlcdrv.c unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; mask5 177 drivers/net/hamradio/hdlcdrv.c mask4 = 0x1f800, mask5 = 0xf800, mask6 = 0xffff; mask5 180 drivers/net/hamradio/hdlcdrv.c mask5 <<= 1, mask6 = (mask6 << 1) | 1) { mask5 196 drivers/net/hamradio/hdlcdrv.c } else if ((s->hdlcrx.bitstream & mask4) == mask5) {