mask1 56 arch/alpha/kernel/sys_dp264.c unsigned long mask0, mask1, mask2, mask3, dummy; mask1 60 arch/alpha/kernel/sys_dp264.c mask1 = mask & cpu_irq_affinity[1]; mask1 65 arch/alpha/kernel/sys_dp264.c else if (bcpu == 1) mask1 |= isa_enable; mask1 79 arch/alpha/kernel/sys_dp264.c *dim1 = mask1; mask1 103 arch/alpha/kernel/sys_rawhide.c unsigned int mask, mask1, hose; mask1 112 arch/alpha/kernel/sys_rawhide.c mask1 = 1 << irq; mask1 113 arch/alpha/kernel/sys_rawhide.c mask = ~mask1 | hose_irq_masks[hose]; mask1 122 arch/alpha/kernel/sys_rawhide.c *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; mask1 70 arch/alpha/kernel/sys_titan.c unsigned long mask0, mask1, mask2, mask3, dummy; mask1 75 arch/alpha/kernel/sys_titan.c mask1 = mask & titan_cpu_irq_affinity[1]; mask1 80 arch/alpha/kernel/sys_titan.c else if (bcpu == 1) mask1 |= isa_enable; mask1 94 arch/alpha/kernel/sys_titan.c *dim1 = mask1; mask1 133 arch/mips/sgi-ip27/ip27-nmi.c u64 mask0, mask1, pend0, pend1; mask1 137 arch/mips/sgi-ip27/ip27-nmi.c mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); mask1 140 arch/mips/sgi-ip27/ip27-nmi.c mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); mask1 146 arch/mips/sgi-ip27/ip27-nmi.c pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); mask1 615 arch/mips/vr41xx/common/icu.c uint16_t mask1, mask2; mask1 619 arch/mips/vr41xx/common/icu.c mask1 = icu1_read(MSYSINT1REG); mask1 624 arch/mips/vr41xx/common/icu.c mask1 &= pend1; mask1 627 arch/mips/vr41xx/common/icu.c if (mask1) { mask1 629 arch/mips/vr41xx/common/icu.c if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i))) mask1 28 arch/parisc/kernel/sys_parisc32.c compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, mask1 32 arch/parisc/kernel/sys_parisc32.c ((__u64)mask1 << 32) | mask0, mask1 461 arch/x86/events/intel/uncore_snbep.c DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63"); mask1 942 drivers/acpi/acpi_lpss.c u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; mask1 979 drivers/acpi/acpi_lpss.c LPSS_IOSF_GPIODEF0, value1, mask1); mask1 991 drivers/acpi/acpi_lpss.c u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; mask1 1003 drivers/acpi/acpi_lpss.c LPSS_IOSF_GPIODEF0, value1, mask1); mask1 439 drivers/clk/bcm/clk-bcm2835.c u32 mask1; mask1 449 drivers/clk/bcm/clk-bcm2835.c .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK, mask1 459 drivers/clk/bcm/clk-bcm2835.c .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK, mask1 689 drivers/clk/bcm/clk-bcm2835.c ana[1] &= ~data->ana->mask1; mask1 1039 drivers/edac/amd64_edac.c u32 *mask1 = &pvt->csels[1].csmasks[cs]; mask1 1048 drivers/edac/amd64_edac.c if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) mask1 1050 drivers/edac/amd64_edac.c cs, *mask1, (pvt->fam == 0x10) ? reg1 mask1 888 drivers/edac/i5100_edac.c u16 mask1; mask1 911 drivers/edac/i5100_edac.c mask1 = priv->inject_eccmask2; mask1 915 drivers/edac/i5100_edac.c pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1); mask1 918 drivers/edac/i5100_edac.c pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1); mask1 59 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, mask1 67 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value1, mask1, shift1); mask1 82 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, mask1 91 drivers/gpu/drm/amd/display/dc/dc_helper.c set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, mask1 105 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, mask1 113 drivers/gpu/drm/amd/display/dc/dc_helper.c set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, mask1 152 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 156 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 162 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 167 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 174 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 180 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 188 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 195 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 204 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 212 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 222 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 231 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 242 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 252 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); mask1 359 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, mask1 369 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); mask1 136 drivers/gpu/drm/amd/display/dc/dm_services.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); mask1 140 drivers/gpu/drm/amd/display/dc/dm_services.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); mask1 395 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 399 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 404 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 410 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 417 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 425 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 434 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, mask1 485 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, mask1 105 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ mask1 108 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 110 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 111 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ mask1 186 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ mask1 189 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 191 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 192 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ mask1 188 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ mask1 191 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 193 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 194 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ mask1 184 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ mask1 187 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 189 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ mask1 190 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ mask1 1030 drivers/gpu/drm/msm/edp/edp_ctrl.c u32 isr1, isr2, mask1, mask2; mask1 1038 drivers/gpu/drm/msm/edp/edp_ctrl.c mask1 = isr1 & EDP_INTR_MASK1; mask1 1041 drivers/gpu/drm/msm/edp/edp_ctrl.c isr1 &= ~mask1; /* remove masks bit */ mask1 1045 drivers/gpu/drm/msm/edp/edp_ctrl.c isr1, mask1, isr2, mask2); mask1 1049 drivers/gpu/drm/msm/edp/edp_ctrl.c ack |= mask1; mask1 682 drivers/iio/adc/twl6030-gpadc.c unsigned int reg1, unsigned int mask0, unsigned int mask1, mask1 688 drivers/iio/adc/twl6030-gpadc.c val |= (trim_regs[reg1] & mask1) >> 1; mask1 14116 drivers/infiniband/hw/hfi1/chip.c u32 mask1; mask1 14177 drivers/infiniband/hw/hfi1/chip.c (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT | mask1 14302 drivers/infiniband/hw/hfi1/chip.c rrd.mask1 = LRH_BTH_MASK; mask1 14384 drivers/infiniband/hw/hfi1/chip.c rrd.mask1 = 1; mask1 14442 drivers/infiniband/hw/hfi1/chip.c rrd.mask1 = L2_TYPE_MASK; mask1 92 drivers/irqchip/irq-sirfsoc.c u32 mask1; mask1 104 drivers/irqchip/irq-sirfsoc.c sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); mask1 116 drivers/irqchip/irq-sirfsoc.c writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); mask1 163 drivers/mfd/menelaus.c u8 mask1, mask2; mask1 201 drivers/mfd/menelaus.c the_menelaus->mask1 &= ~(1 << irq); mask1 203 drivers/mfd/menelaus.c the_menelaus->mask1); mask1 215 drivers/mfd/menelaus.c the_menelaus->mask1 |= (1 << irq); mask1 217 drivers/mfd/menelaus.c the_menelaus->mask1); mask1 772 drivers/mfd/menelaus.c & ~menelaus->mask1; mask1 1181 drivers/mfd/menelaus.c menelaus->mask1 = 0xff; mask1 125 drivers/net/can/pch_can.c u32 mask1; mask1 333 drivers/net/can/pch_can.c iowrite32(0xffff, &priv->regs->ifregs[0].mask1); mask1 371 drivers/net/can/pch_can.c iowrite32(0, &priv->regs->ifregs[0].mask1); mask1 394 drivers/net/can/pch_can.c iowrite32(0, &priv->regs->ifregs[1].mask1); mask1 1756 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u64 mask0, u64 mask1, unsigned int crc, bool enable); mask1 490 drivers/net/ethernet/freescale/fman/fman_memac.c u64 mask1, mask2; mask1 495 drivers/net/ethernet/freescale/fman/fman_memac.c mask1 = eth_addr & (u64)0x01; mask1 500 drivers/net/ethernet/freescale/fman/fman_memac.c mask1 ^= mask2; mask1 504 drivers/net/ethernet/freescale/fman/fman_memac.c xor_val |= (mask1 << (5 - i)); mask1 158 drivers/net/hamradio/hdlcdrv.c unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; mask1 176 drivers/net/hamradio/hdlcdrv.c for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, mask1 179 drivers/net/hamradio/hdlcdrv.c i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, mask1 181 drivers/net/hamradio/hdlcdrv.c if ((s->hdlcrx.bitstream & mask1) == mask1) mask1 254 drivers/net/hamradio/hdlcdrv.c unsigned int mask1, mask2, mask3; mask1 329 drivers/net/hamradio/hdlcdrv.c mask1 = 0x1f000; mask1 333 drivers/net/hamradio/hdlcdrv.c for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, mask1 335 drivers/net/hamradio/hdlcdrv.c if ((s->hdlctx.bitstream & mask1) != mask1) mask1 519 drivers/pcmcia/i82365.c u_int mask1 = 0; mask1 533 drivers/pcmcia/i82365.c mask1 |= (1 << i); mask1 535 drivers/pcmcia/i82365.c if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0)) mask1 536 drivers/pcmcia/i82365.c mask1 ^= (1 << i); mask1 540 drivers/pcmcia/i82365.c if (mask1) { mask1 546 drivers/pcmcia/i82365.c mask1 |= (1 << i); mask1 554 drivers/pcmcia/i82365.c if (mask1 & (1<<i)) mask1 555 drivers/pcmcia/i82365.c printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); mask1 556 drivers/pcmcia/i82365.c if (mask1 == 0) printk("none!"); mask1 558 drivers/pcmcia/i82365.c return mask1; mask1 241 drivers/pcmcia/tcic.c u_int mask1; mask1 252 drivers/pcmcia/tcic.c mask1 = 0; mask1 256 drivers/pcmcia/tcic.c mask1 |= (1 << i); mask1 258 drivers/pcmcia/tcic.c if ((mask1 & (1 << i)) && (try_irq(i) != 0)) { mask1 259 drivers/pcmcia/tcic.c mask1 ^= (1 << i); mask1 263 drivers/pcmcia/tcic.c if (mask1) { mask1 270 drivers/pcmcia/tcic.c mask1 |= (1 << i); mask1 278 drivers/pcmcia/tcic.c if (mask1 & (1<<i)) mask1 279 drivers/pcmcia/tcic.c printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); mask1 282 drivers/pcmcia/tcic.c return mask1; mask1 854 drivers/power/supply/rt9455_charger.c unsigned int irq1, mask1, mask2; mask1 866 drivers/power/supply/rt9455_charger.c ret = regmap_read(info->regmap, RT9455_REG_MASK1, &mask1); mask1 887 drivers/power/supply/rt9455_charger.c if ((mask1 & GET_MASK(F_BATABM)) == 0) { mask1 1500 drivers/power/supply/rt9455_charger.c unsigned int irq1, mask1; mask1 1522 drivers/power/supply/rt9455_charger.c ret = regmap_read(info->regmap, RT9455_REG_MASK1, &mask1); mask1 1528 drivers/power/supply/rt9455_charger.c if (mask1 & GET_MASK(F_BATABM)) { mask1 250 drivers/soc/fsl/qe/gpio.c u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); mask1 265 drivers/soc/fsl/qe/gpio.c if (sregs->cpdata & mask1) mask1 266 drivers/soc/fsl/qe/gpio.c qe_gc->cpdata |= mask1; mask1 268 drivers/soc/fsl/qe/gpio.c qe_gc->cpdata &= ~mask1; mask1 271 drivers/soc/fsl/qe/gpio.c clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); mask1 561 drivers/staging/most/dim2/hal.c u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) | mask1 567 drivers/staging/most/dim2/hal.c return (readl(&g.dim2->MLBC1) & mask1) == 0 && mask1 1031 drivers/tty/nozomi.c u16 read_iir, u16 mask1, u16 mask2) mask1 1033 drivers/tty/nozomi.c if (*toggle == 0 && read_iir & mask1) { mask1 1035 drivers/tty/nozomi.c writew(mask1, dc->reg_fcr); mask1 1051 drivers/tty/nozomi.c if (read_iir & mask1) { mask1 1053 drivers/tty/nozomi.c writew(mask1, dc->reg_fcr); mask1 1607 drivers/usb/host/r8a66597-hcd.c u16 mask0, mask1, mask2; mask1 1620 drivers/usb/host/r8a66597-hcd.c mask1 = intsts1 & intenb1; mask1 1642 drivers/usb/host/r8a66597-hcd.c if (mask1) { mask1 1643 drivers/usb/host/r8a66597-hcd.c if (mask1 & ATTCH) { mask1 1650 drivers/usb/host/r8a66597-hcd.c if (mask1 & DTCH) { mask1 1655 drivers/usb/host/r8a66597-hcd.c if (mask1 & BCHG) { mask1 1661 drivers/usb/host/r8a66597-hcd.c if (mask1 & SIGN) { mask1 1666 drivers/usb/host/r8a66597-hcd.c if (mask1 & SACK) { mask1 1117 fs/notify/fanotify/fanotify_user.c __u32, mask0, __u32, mask1, int, dfd, mask1 1122 fs/notify/fanotify/fanotify_user.c ((__u64)mask0 << 32) | mask1, mask1 1124 fs/notify/fanotify/fanotify_user.c ((__u64)mask1 << 32) | mask0, mask1 63 fs/orangefs/orangefs-debugfs.c __u64 mask1; mask1 474 fs/orangefs/orangefs-debugfs.c c_mask.mask1, mask1 561 fs/orangefs/orangefs-debugfs.c (unsigned long long *)&(cdm_array[i].mask1), mask1 772 fs/orangefs/orangefs-debugfs.c if ((mask->mask1 & cdm_array[index].mask1) || mask1 816 fs/orangefs/orangefs-debugfs.c if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && mask1 823 fs/orangefs/orangefs-debugfs.c if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && mask1 892 fs/orangefs/orangefs-debugfs.c (**sane_mask).mask1 = (**sane_mask).mask1 | cdm_array[i].mask1; mask1 917 fs/orangefs/orangefs-debugfs.c client_debug_mask.mask1 = mask2_info.mask1_value; mask1 923 fs/orangefs/orangefs-debugfs.c (unsigned long long)client_debug_mask.mask1, mask1 203 include/linux/cpumask.h #define for_each_cpu_and(cpu, mask1, mask2) \ mask1 204 include/linux/cpumask.h for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask1, (void)mask2) mask1 304 include/linux/cpumask.h #define for_each_cpu_and(cpu, mask1, mask2) \ mask1 306 include/linux/cpumask.h (cpu) = cpumask_next_and((cpu), (mask1), (mask2)), \ mask1 620 include/linux/cpumask.h #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) mask1 532 include/linux/nodemask.h nodemask_t mask1; mask1 87 include/uapi/linux/serial.h unsigned char mask1, match1; mask1 212 mm/mempolicy.c nodes_and(nsc->mask1, mask1 220 mm/mempolicy.c mpol_relative_nodemask(&nsc->mask2, nodes, &nsc->mask1); mask1 222 mm/mempolicy.c nodes_and(nsc->mask2, *nodes, nsc->mask1); mask1 1474 mm/mempolicy.c old = &scratch->mask1; mask1 1229 sound/isa/es18xx.c unsigned char val1, val2, mask1, mask2; mask1 1239 sound/isa/es18xx.c mask1 = mask << shift_left; mask1 1243 sound/isa/es18xx.c if (snd_es18xx_reg_bits(chip, left_reg, mask1, val1) != val1) mask1 1248 sound/isa/es18xx.c change = (snd_es18xx_reg_bits(chip, left_reg, mask1 | mask2, mask1 1283 sound/pci/es1938.c unsigned char val1, val2, mask1, mask2; mask1 1293 sound/pci/es1938.c mask1 = mask << shift_left; mask1 1297 sound/pci/es1938.c if (snd_es1938_reg_bits(chip, left_reg, mask1, val1) != val1) mask1 1302 sound/pci/es1938.c change = (snd_es1938_reg_bits(chip, left_reg, mask1 | mask2, mask1 174 sound/pci/ice1712/delta.c unsigned char tmp, mask1, mask2; mask1 177 sound/pci/ice1712/delta.c mask1 = ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK; mask1 182 sound/pci/ice1712/delta.c tmp &= ~(mask1 | mask2); mask1 187 sound/pci/ice1712/delta.c tmp |= mask1; mask1 191 sound/pci/ice1712/delta.c tmp &= ~mask1; mask1 36 sound/pci/ice1712/wm8766.c .mask1 = WM8766_VOL_MASK, mask1 47 sound/pci/ice1712/wm8766.c .mask1 = WM8766_VOL_MASK, mask1 58 sound/pci/ice1712/wm8766.c .mask1 = WM8766_VOL_MASK, mask1 67 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_MUTE1, mask1 74 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_MUTE2, mask1 81 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_MUTE3, mask1 88 sound/pci/ice1712/wm8766.c .mask1 = WM8766_PHASE_INVERT1, mask1 94 sound/pci/ice1712/wm8766.c .mask1 = WM8766_PHASE_INVERT2, mask1 100 sound/pci/ice1712/wm8766.c .mask1 = WM8766_PHASE_INVERT3, mask1 106 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_DEEMP1, mask1 112 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_DEEMP2, mask1 118 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_DEEMP3, mask1 124 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC_IZD, mask1 130 sound/pci/ice1712/wm8766.c .mask1 = WM8766_DAC2_ZCD, mask1 215 sound/pci/ice1712/wm8766.c val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; mask1 216 sound/pci/ice1712/wm8766.c val1 >>= __ffs(wm->ctl[n].mask1); mask1 253 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; mask1 254 sound/pci/ice1712/wm8766.c val |= regval1 << __ffs(wm->ctl[n].mask1); mask1 124 sound/pci/ice1712/wm8766.h u16 reg1, reg2, mask1, mask2, min, max, flags; mask1 139 sound/pci/ice1712/wm8776.c .mask1 = WM8776_DACVOL_MASK, mask1 149 sound/pci/ice1712/wm8776.c .mask1 = WM8776_DAC_PL_LL, mask1 157 sound/pci/ice1712/wm8776.c .mask1 = WM8776_DAC_DZCEN, mask1 165 sound/pci/ice1712/wm8776.c .mask1 = WM8776_HPVOL_MASK, mask1 175 sound/pci/ice1712/wm8776.c .mask1 = WM8776_PWR_HPPD, mask1 183 sound/pci/ice1712/wm8776.c .mask1 = WM8776_VOL_HPZCEN, mask1 191 sound/pci/ice1712/wm8776.c .mask1 = WM8776_OUTMUX_AUX, mask1 197 sound/pci/ice1712/wm8776.c .mask1 = WM8776_OUTMUX_BYPASS, mask1 203 sound/pci/ice1712/wm8776.c .mask1 = WM8776_DAC_IZD, mask1 210 sound/pci/ice1712/wm8776.c .mask1 = WM8776_PHASE_INVERTL, mask1 218 sound/pci/ice1712/wm8776.c .mask1 = WM8776_DAC2_DEEMPH, mask1 226 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_GAIN_MASK, mask1 236 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_MUTEL, mask1 244 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_MUX_AIN1, mask1 250 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_MUX_AIN2, mask1 256 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_MUX_AIN3, mask1 262 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_MUX_AIN4, mask1 268 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ADC_MUX_AIN5, mask1 284 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC1_LCT_MASK, mask1 295 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC3_ATK_MASK, mask1 306 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC3_DCY_MASK, mask1 316 sound/pci/ice1712/wm8776.c .mask1 = WM8776_LIM_TRANWIN_MASK, mask1 324 sound/pci/ice1712/wm8776.c .mask1 = WM8776_LIM_MAXATTEN_MASK, mask1 334 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC1_LCT_MASK, mask1 346 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC3_ATK_MASK, mask1 357 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC3_DCY_MASK, mask1 365 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC1_MAXGAIN_MASK, mask1 375 sound/pci/ice1712/wm8776.c .mask1 = WM8776_LIM_MAXATTEN_MASK, mask1 389 sound/pci/ice1712/wm8776.c .mask1 = WM8776_ALC2_HOLD_MASK, mask1 396 sound/pci/ice1712/wm8776.c .mask1 = WM8776_NGAT_ENABLE, mask1 404 sound/pci/ice1712/wm8776.c .mask1 = WM8776_NGAT_THR_MASK, mask1 489 sound/pci/ice1712/wm8776.c val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; mask1 490 sound/pci/ice1712/wm8776.c val1 >>= __ffs(wm->ctl[n].mask1); mask1 527 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; mask1 528 sound/pci/ice1712/wm8776.c val |= regval1 << __ffs(wm->ctl[n].mask1); mask1 180 sound/pci/ice1712/wm8776.h u16 reg1, reg2, mask1, mask2, min, max, flags; mask1 1374 sound/pci/rme9652/rme9652.c unsigned int mask1, mask2, val; mask1 1377 sound/pci/rme9652/rme9652.c case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break; mask1 1378 sound/pci/rme9652/rme9652.c case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break; mask1 1379 sound/pci/rme9652/rme9652.c case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break; mask1 1383 sound/pci/rme9652/rme9652.c ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0; mask1 966 sound/soc/codecs/cs35l33.c unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2; mask1 973 sound/soc/codecs/cs35l33.c regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1); mask1 978 sound/soc/codecs/cs35l33.c if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2)) mask1 866 sound/soc/codecs/cs35l34.c unsigned int mask1, mask2, mask3, mask4, current1; mask1 878 sound/soc/codecs/cs35l34.c regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1); mask1 880 sound/soc/codecs/cs35l34.c if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3) mask1 1112 sound/soc/codecs/cs35l35.c unsigned int mask1, mask2, mask3, mask4, current1; mask1 1123 sound/soc/codecs/cs35l35.c regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1); mask1 1126 sound/soc/codecs/cs35l35.c if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3) mask1 2631 sound/soc/codecs/rt5665.c unsigned int val1, val2, mask1 = 0, mask2 = 0; mask1 2635 sound/soc/codecs/rt5665.c mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK | mask1 2641 sound/soc/codecs/rt5665.c mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK | mask1 2649 sound/soc/codecs/rt5665.c mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK | mask1 2659 sound/soc/codecs/rt5665.c if (mask1) mask1 2661 sound/soc/codecs/rt5665.c mask1, val1); mask1 2667 sound/soc/codecs/rt5665.c if (mask1) mask1 2669 sound/soc/codecs/rt5665.c mask1, 0); mask1 68 tools/usb/usbip/libsrc/names.c unsigned int mask1 = HASH1 << 27, mask2 = HASH2 << 27; mask1 70 tools/usb/usbip/libsrc/names.c for (; mask1 >= HASH1; mask1 >>= 1, mask2 >>= 1) mask1 71 tools/usb/usbip/libsrc/names.c if (num & mask1)