m_n               974 drivers/gpu/drm/gma500/cdv_intel_dp.c 		     struct cdv_intel_dp_m_n *m_n)
m_n               976 drivers/gpu/drm/gma500/cdv_intel_dp.c 	m_n->tu = 64;
m_n               977 drivers/gpu/drm/gma500/cdv_intel_dp.c 	m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
m_n               978 drivers/gpu/drm/gma500/cdv_intel_dp.c 	m_n->gmch_n = link_clock * nlanes;
m_n               979 drivers/gpu/drm/gma500/cdv_intel_dp.c 	cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
m_n               980 drivers/gpu/drm/gma500/cdv_intel_dp.c 	m_n->link_m = pixel_clock;
m_n               981 drivers/gpu/drm/gma500/cdv_intel_dp.c 	m_n->link_n = link_clock;
m_n               982 drivers/gpu/drm/gma500/cdv_intel_dp.c 	cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
m_n               995 drivers/gpu/drm/gma500/cdv_intel_dp.c 	struct cdv_intel_dp_m_n m_n;
m_n              1026 drivers/gpu/drm/gma500/cdv_intel_dp.c 			     mode->clock, adjusted_mode->clock, &m_n);
m_n              1030 drivers/gpu/drm/gma500/cdv_intel_dp.c 			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
m_n              1031 drivers/gpu/drm/gma500/cdv_intel_dp.c 			   m_n.gmch_m);
m_n              1032 drivers/gpu/drm/gma500/cdv_intel_dp.c 		REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
m_n              1033 drivers/gpu/drm/gma500/cdv_intel_dp.c 		REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
m_n              1034 drivers/gpu/drm/gma500/cdv_intel_dp.c 		REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
m_n               129 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	u32 m_n = 0;
m_n               159 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 		m_n = (temp % (u64)1000000000) / (u64)100000000;
m_n               162 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 			if (m_n * 6 >= 50) {
m_n               165 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 			} else if (m_n * 6 >= 30) {
m_n               173 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 			if (m_n * 6 >= 50) {
m_n               176 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 			} else if (m_n * 6 >= 30) {
m_n               179 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 			} else if (m_n * 6 >= 10) {
m_n               128 drivers/gpu/drm/i915/display/intel_display.c 					 const struct intel_link_m_n *m_n,
m_n              7526 drivers/gpu/drm/i915/display/intel_display.c 		       struct intel_link_m_n *m_n,
m_n              7534 drivers/gpu/drm/i915/display/intel_display.c 	m_n->tu = 64;
m_n              7537 drivers/gpu/drm/i915/display/intel_display.c 		    &m_n->gmch_m, &m_n->gmch_n,
m_n              7541 drivers/gpu/drm/i915/display/intel_display.c 		    &m_n->link_m, &m_n->link_n,
m_n              7620 drivers/gpu/drm/i915/display/intel_display.c 					 const struct intel_link_m_n *m_n)
m_n              7626 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
m_n              7627 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
m_n              7628 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
m_n              7629 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
m_n              7646 drivers/gpu/drm/i915/display/intel_display.c 					 const struct intel_link_m_n *m_n,
m_n              7655 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
m_n              7656 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
m_n              7657 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
m_n              7658 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
m_n              7672 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
m_n              7673 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
m_n              7674 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
m_n              7675 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
m_n              7679 drivers/gpu/drm/i915/display/intel_display.c void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
m_n              7683 drivers/gpu/drm/i915/display/intel_display.c 	if (m_n == M1_N1) {
m_n              7686 drivers/gpu/drm/i915/display/intel_display.c 	} else if (m_n == M2_N2) {
m_n              9690 drivers/gpu/drm/i915/display/intel_display.c 					 struct intel_link_m_n *m_n)
m_n              9696 drivers/gpu/drm/i915/display/intel_display.c 	m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
m_n              9697 drivers/gpu/drm/i915/display/intel_display.c 	m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
m_n              9698 drivers/gpu/drm/i915/display/intel_display.c 	m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
m_n              9700 drivers/gpu/drm/i915/display/intel_display.c 	m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
m_n              9701 drivers/gpu/drm/i915/display/intel_display.c 	m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
m_n              9707 drivers/gpu/drm/i915/display/intel_display.c 					 struct intel_link_m_n *m_n,
m_n              9714 drivers/gpu/drm/i915/display/intel_display.c 		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
m_n              9715 drivers/gpu/drm/i915/display/intel_display.c 		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
m_n              9716 drivers/gpu/drm/i915/display/intel_display.c 		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
m_n              9718 drivers/gpu/drm/i915/display/intel_display.c 		m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
m_n              9719 drivers/gpu/drm/i915/display/intel_display.c 		m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
m_n              9732 drivers/gpu/drm/i915/display/intel_display.c 		m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
m_n              9733 drivers/gpu/drm/i915/display/intel_display.c 		m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
m_n              9734 drivers/gpu/drm/i915/display/intel_display.c 		m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
m_n              9736 drivers/gpu/drm/i915/display/intel_display.c 		m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
m_n              9737 drivers/gpu/drm/i915/display/intel_display.c 		m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
m_n              11374 drivers/gpu/drm/i915/display/intel_display.c 			     const struct intel_link_m_n *m_n)
m_n              11386 drivers/gpu/drm/i915/display/intel_display.c 	if (!m_n->link_n)
m_n              11389 drivers/gpu/drm/i915/display/intel_display.c 	return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
m_n              11966 drivers/gpu/drm/i915/display/intel_display.c 		      const struct intel_link_m_n *m_n)
m_n              11970 drivers/gpu/drm/i915/display/intel_display.c 		      m_n->gmch_m, m_n->gmch_n,
m_n              11971 drivers/gpu/drm/i915/display/intel_display.c 		      m_n->link_m, m_n->link_n, m_n->tu);
m_n              12460 drivers/gpu/drm/i915/display/intel_display.c intel_compare_link_m_n(const struct intel_link_m_n *m_n,
m_n              12464 drivers/gpu/drm/i915/display/intel_display.c 	return m_n->tu == m2_n2->tu &&
m_n              12465 drivers/gpu/drm/i915/display/intel_display.c 		intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
m_n              12467 drivers/gpu/drm/i915/display/intel_display.c 		intel_compare_m_n(m_n->link_m, m_n->link_n,
m_n               416 drivers/gpu/drm/i915/display/intel_display.h 			    struct intel_link_m_n *m_n,
m_n               501 drivers/gpu/drm/i915/display/intel_display.h 		      enum link_m_n_set m_n);
m_n               504 drivers/gpu/drm/i915/display/intel_display.h int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);