m_io 3807 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3815 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3823 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3882 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3890 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3898 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3944 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 3952 arch/x86/include/asm/uv/uv_mmrs.h unsigned long m_io:6; /* RW */ m_io 832 arch/x86/kernel/apic/x2apic_uv_x.c int i, n, shift, m_io, max_io; m_io 842 arch/x86/kernel/apic/x2apic_uv_x.c m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK) m_io 853 arch/x86/kernel/apic/x2apic_uv_x.c m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK) m_io 859 arch/x86/kernel/apic/x2apic_uv_x.c pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io); m_io 902 arch/x86/kernel/apic/x2apic_uv_x.c addr1 = (base << shift) + f * (1ULL << m_io); m_io 903 arch/x86/kernel/apic/x2apic_uv_x.c addr2 = (base << shift) + (l + 1) * (1ULL << m_io); m_io 912 arch/x86/kernel/apic/x2apic_uv_x.c pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io); m_io 915 arch/x86/kernel/apic/x2apic_uv_x.c map_high(id, base, shift, m_io, max_io, map_uc); m_io 922 arch/x86/kernel/apic/x2apic_uv_x.c int shift, enable, m_io, n_io; m_io 937 arch/x86/kernel/apic/x2apic_uv_x.c m_io = mmioh.s1.m_io; m_io 945 arch/x86/kernel/apic/x2apic_uv_x.c m_io = mmioh.s2.m_io; m_io 953 arch/x86/kernel/apic/x2apic_uv_x.c pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode); m_io 954 arch/x86/kernel/apic/x2apic_uv_x.c map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);