m4u_dom           265 drivers/iommu/mtk_iommu.c 	struct mtk_iommu_domain *dom = data->m4u_dom;
m4u_dom           408 drivers/iommu/mtk_iommu.c 	if (!data->m4u_dom) {
m4u_dom           409 drivers/iommu/mtk_iommu.c 		data->m4u_dom = dom;
m4u_dom           803 drivers/iommu/mtk_iommu.c 	struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
m4u_dom           820 drivers/iommu/mtk_iommu.c 	if (m4u_dom)
m4u_dom           821 drivers/iommu/mtk_iommu.c 		writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
m4u_dom            57 drivers/iommu/mtk_iommu.h 	struct mtk_iommu_domain		*m4u_dom;
m4u_dom           163 drivers/iommu/mtk_iommu_v1.c 	struct mtk_iommu_domain *dom = data->m4u_dom;
m4u_dom           223 drivers/iommu/mtk_iommu_v1.c 	struct mtk_iommu_domain *dom = data->m4u_dom;
m4u_dom           273 drivers/iommu/mtk_iommu_v1.c 	if (!data->m4u_dom) {
m4u_dom           274 drivers/iommu/mtk_iommu_v1.c 		data->m4u_dom = dom;
m4u_dom           277 drivers/iommu/mtk_iommu_v1.c 			data->m4u_dom = NULL;
m4u_dom           679 drivers/iommu/mtk_iommu_v1.c 	writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);