m2div_rem        2703 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
m2div_rem        2731 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	m2div_rem = dco_khz % (refclk_khz * m1div);
m2div_rem        2733 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	tmp = (u64)m2div_rem * (1 << 22);
m2div_rem        2780 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	feedfwgain = (use_ssc || m2div_rem > 0) ?
m2div_rem        2804 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
m2div_rem        2824 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (use_ssc || m2div_rem > 0)