m2_n2 129 drivers/gpu/drm/i915/display/intel_display.c const struct intel_link_m_n *m2_n2); m2_n2 7647 drivers/gpu/drm/i915/display/intel_display.c const struct intel_link_m_n *m2_n2) m2_n2 7663 drivers/gpu/drm/i915/display/intel_display.c if (m2_n2 && crtc_state->has_drrs && m2_n2 7666 drivers/gpu/drm/i915/display/intel_display.c TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); m2_n2 7667 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); m2_n2 7668 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); m2_n2 7669 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); m2_n2 9708 drivers/gpu/drm/i915/display/intel_display.c struct intel_link_m_n *m2_n2) m2_n2 9722 drivers/gpu/drm/i915/display/intel_display.c if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { m2_n2 9723 drivers/gpu/drm/i915/display/intel_display.c m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); m2_n2 9724 drivers/gpu/drm/i915/display/intel_display.c m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); m2_n2 9725 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) m2_n2 9727 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); m2_n2 9728 drivers/gpu/drm/i915/display/intel_display.c m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) m2_n2 12461 drivers/gpu/drm/i915/display/intel_display.c const struct intel_link_m_n *m2_n2, m2_n2 12464 drivers/gpu/drm/i915/display/intel_display.c return m_n->tu == m2_n2->tu && m2_n2 12466 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_m, m2_n2->gmch_n, exact) && m2_n2 12468 drivers/gpu/drm/i915/display/intel_display.c m2_n2->link_m, m2_n2->link_n, exact);