m2_int 1411 drivers/gpu/drm/i915/display/intel_ddi.c u32 m1, m2_int, m2_frac, div1, div2, ref_clock; m2_int 1417 drivers/gpu/drm/i915/display/intel_ddi.c m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; m2_int 1453 drivers/gpu/drm/i915/display/intel_ddi.c tmp = (u64)m1 * m2_int * ref_clock + m2_int 1729 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 m2_int; m2_int 1771 drivers/gpu/drm/i915/display/intel_dpll_mgr.c clk_div->m2_int = best_clock.m2 >> 22; m2_int 1841 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll0 = clk_div->m2_int;