m2_frac          1411 drivers/gpu/drm/i915/display/intel_ddi.c 	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
m2_frac          1418 drivers/gpu/drm/i915/display/intel_ddi.c 	m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
m2_frac          1454 drivers/gpu/drm/i915/display/intel_ddi.c 	      (((u64)m1 * m2_frac * ref_clock) >> 22);
m2_frac          1730 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 m2_frac;
m2_frac          1772 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
m2_frac          1773 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	clk_div->m2_frac_en = clk_div->m2_frac != 0;
m2_frac          1843 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	dpll_hw_state->pll2 = clk_div->m2_frac;