lvds_ss_gen_cntl 1109 drivers/gpu/drm/radeon/radeon_combios.c 	uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
lvds_ss_gen_cntl 1124 drivers/gpu/drm/radeon/radeon_combios.c 	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
lvds_ss_gen_cntl 1125 drivers/gpu/drm/radeon/radeon_combios.c 	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
lvds_ss_gen_cntl  191 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
lvds_ss_gen_cntl  198 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
lvds_ss_gen_cntl  211 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
lvds_ss_gen_cntl  213 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
lvds_ss_gen_cntl  242 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);